S. Sheu, Z. H. Lin, C. S. Lin, J. Lau, S. H. Lee, K. Su, T. Ku, S. H. Wu, J. Hung, P. S. Chen, S. Lai, W. Lo, M. Kao
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引用次数: 2
Abstract
In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMC's 0.18μm process (FEOL) and ITRI's BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.
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