Session Objective: Identify various tools and practices that can reduce the risk of and mitigate the impact of digital safety challenges faced by online communities
会议目标:确定各种工具和实践，可以降低在线社区面临的数字安全挑战的风险和影响
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Pub Date : 2018-10-03DOI: 10.1007/978-1-4899-6934-7_4
S. Sangwine
{"title":"Power sources and power supplies","authors":"S. Sangwine","doi":"10.1007/978-1-4899-6934-7_4","DOIUrl":"https://doi.org/10.1007/978-1-4899-6934-7_4","url":null,"abstract":"","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"65 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2018-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90225006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-27DOI: 10.1109/ECTC.2014.6897512
Zhang Weihong, Hong Shengping, Yang Xiaolong, Zhou Feng, Lu Hailun, Sheng Haijun, Z. Tong-long
Recently, TCNCP (Thermal Compression with Non-Conductive Paste) flip chip technology has been adopted for various devices because of high demand for large bump density. Fine pitch micro Cu bumps are usually connected to trace on the substrate (Bump on Trace, BOT) due to space limitation on substrate. In this study, TCNCP technology was used to attach die onto substrate trace with surface finish of thin Ni (0.1um) and thick Au (0.4um). The micro Cu bump used in the device under test has a dome shaped Sn-based solder cap of 13um in height. The ratio of Au layer plated on the substrate trace to Sn cap on the Cu bump is about 10 wt%, which is far beyond threshold value of 3 wt% for Au embrittlement. However, it was proved that the micro joint obtained with TCNCP can pass TCT 1000 cycles, HTS 1000hours and uHAST 192hrs without failure. SEM/EDX study on HTS samples (0hr, 500hr, 1000hr) showed that the joints had a large amount of IMC formed mainly consisting of (CuxAu1-x)6Sn5 phase after reflow and independent Cu3Sn phase formed near to die bump at a later stage during HTS test. Although AuSn4 was present in 0hr sample, it disappeared later. No Ni was detected. Phase segregation appeared near to die bump when HTS time went up to 1000hrs. No crack and void were found at that point.
近年来，由于对大碰撞密度的高要求，TCNCP (Thermal Compression with Non-Conductive Paste)倒装芯片技术已被广泛应用于各种器件。由于衬底空间的限制，通常采用细间距微铜凸点连接到衬底上的迹线(Bump on trace, BOT)。在本研究中，采用TCNCP技术将模具贴合在基片上，表面光洁度为薄Ni (0.1um)和厚Au (0.4um)。在测试设备中使用的微铜凸点具有13um高度的球形锡基焊帽。镀在基体痕迹上的Au层与Cu凸起处的Sn帽的比例约为10 wt%，远远超过了Au脆化的阈值3 wt%。实验证明，采用TCNCP制备的微接头可通过TCT 1000次、HTS 1000小时和uHAST 192小时而不失效。对HTS样品(0hr, 500hr, 1000hr)的SEM/EDX研究表明，在HTS测试过程中，接头在回流后形成了大量的IMC，主要由(CuxAu1-x)6Sn5相组成，在后期靠近凹模处形成了独立的Cu3Sn相。虽然在0hr样品中存在AuSn4，但随后就消失了。未检测到Ni。当高温加热时间达到1000hrs时，在凹模附近出现了相偏析。此时未发现裂纹和空洞。
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