10-T Full Subtraction Logic Using GDI Technique

Abstract

Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been reported. Layout design for the best optimum ciruit is designed using Cadence Layout XL.