A design methodology for modelling CMOS gates based on Petri nets

Abstract

A design methodology for deriving switch level equivalent circuits for CMOS combinational logic circuits based on Petri nets is presented. Detailed Petri net models of the p- and n-type transistors are discussed, and the use of these models to construct the CMOS gates (i.e., NOT, NAND, NOR) for logic correctness is illustrated. How the proposed methodology can be extended to include timing verification is discussed.<>