{"title":"Homeland security video surveillance system utilising the internet of video things for smart cities","authors":"Yasser Ismail, Mohamed Hammad, Mahmoud Darwich, Wael Elmedany","doi":"10.1049/cdt2.12014","DOIUrl":null,"url":null,"abstract":"<p>In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non-standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co-processor that can be used for video surveillance cameras in homeland security. The proposed ME co-processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co-processor is suited for high-efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block-based motion estimation (FSBB-ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB-ME algorithm. Modelism-version10.4a has been used for simulation and time verification testing proposes. The proposed ME co-processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.</p>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"15 4","pages":"302-319"},"PeriodicalIF":1.1000,"publicationDate":"2021-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/cdt2.12014","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cdt2.12014","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 1
Abstract
In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non-standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co-processor that can be used for video surveillance cameras in homeland security. The proposed ME co-processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co-processor is suited for high-efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block-based motion estimation (FSBB-ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB-ME algorithm. Modelism-version10.4a has been used for simulation and time verification testing proposes. The proposed ME co-processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.