Homeland security video surveillance system utilising the internet of video things for smart cities

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2021-04-04 DOI:10.1049/cdt2.12014
Yasser Ismail, Mohamed Hammad, Mahmoud Darwich, Wael Elmedany
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引用次数: 1

Abstract

In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non-standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co-processor that can be used for video surveillance cameras in homeland security. The proposed ME co-processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co-processor is suited for high-efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block-based motion estimation (FSBB-ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB-ME algorithm. Modelism-version10.4a has been used for simulation and time verification testing proposes. The proposed ME co-processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.

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国土安全视频监控系统利用视频物联网为智慧城市
在当今的视频监控系统中,为了保持高安全性和扩大覆盖范围,世界上大多数国家都做了很多努力。部署了许多监视摄像机和传感器,能够在领土的街道和机场发现异常和有意义的事件,这是内部安全的一个方面。影响国土安全系统的主要问题有两个,安全摄像头和传感器不足以覆盖全国所有地区。这是因为视频监控摄像机和传感器安装的成本很高,而且由于提供家庭安全的公司或组织的基础设施不同,安全摄像机和传感器制造的不标准化。介绍了一种用于国土安全视频监控摄像机的运动估计协处理器的设计和硬件实现。如果在视频监控摄像机中采用拟议的ME协处理器,则可以利用视频物联网基础设施(IoVT)进行连接。该协处理器适用于H.265/HEVC高效编码视频监控系统。此外,为了减少内存I/O,在充分利用硬件资源的同时,采用了A级和B级数据重用。此外,在将搜索区域和当前块加载到处理元素数组(PE数组)的过程中,还使用了有效的本地存储器来重用数据。使用主观和定量测量技术计算了所提出架构的性能,并与基于全搜索块的运动估计(FSBB-ME)算法进行了比较。此外,所提出的架构实现了非常高的视频分辨率精度,与FSBB-ME算法的精度相似。Modelism-version10.4a已用于仿真和时间验证测试建议。所提出的ME协处理器可以嵌入到视频监控系统的压缩、解压缩和高清广播中。
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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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