Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program

M. Morsin, M. S. Sulong, Abdul Majeed bin Zulkipli, Tasiransurini Ab Rahman
{"title":"Mask design, fabrication and characterization of in - house n-well MOSFET using spin -on dopant technique for undergraduates program","authors":"M. Morsin, M. S. Sulong, Abdul Majeed bin Zulkipli, Tasiransurini Ab Rahman","doi":"10.1109/ISIEA.2009.5356421","DOIUrl":null,"url":null,"abstract":"This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"13 1","pages":"485-489"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Symposium on Industrial Electronics & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIEA.2009.5356421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

This paper presents a new innovative way of teaching undergraduate program using low cost masks to fabricate n-well MOSFET. The fabrication process of n-well MOSFET started with the establishment of process flow, process modules, and process parameters. The MOSFET fabrication process used blanket-field oxide for isolation, positive resist for lithography process, boron and phosphorus for source/drain doping and aluminum for metallization. An economical solution of masks using transparency films with various channel lengths from 300 µm to 500 µm has been produced to reduce cost. Six layer photolithography masks of MOSFET were designed using AutoCAD drawing tools and then printed using high resolution laser printer on the transparency film. Contact printing method has been utilized to transfer the mask layouts onto a 4-inch silicon wafer using standard photolithography techniques to check the line uniformity. Optical observation using high power microscope shows that the mask layouts were successfully transferred onto photoresist with minimum variation. The n-well CMOS transistors were tested using Keithley 2400 source meter with Lab-view measurement software. The obtained electrical characteristic is same as the theory.
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基于自旋掺杂技术的室内n阱MOSFET掩模设计、制造与表征
本文提出了一种利用低成本掩模制备n阱MOSFET的创新本科教学方法。n阱MOSFET的制造过程从工艺流程、工艺模块和工艺参数的建立开始。MOSFET的制造工艺采用覆盖场氧化物隔离,光刻工艺采用正极抗蚀剂,源/漏极掺杂采用硼和磷,金属化采用铝。为了降低成本,生产了一种经济的掩模解决方案,使用具有300微米至500微米各种通道长度的透明薄膜。利用AutoCAD绘图工具设计了MOSFET的六层光刻掩模,然后使用高分辨率激光打印机在透明膜上打印。采用接触印刷方法将掩模布局转移到4英寸硅片上,使用标准光刻技术检查线条均匀性。高倍显微镜下的光学观察表明,掩模布局以最小的变化成功地转移到光刻胶上。采用Keithley 2400源计和Lab-view测量软件对n阱CMOS晶体管进行了测试。得到的电特性与理论一致。
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