A 60 ns 500×12 0.35µm CMOS low-power scanning read-out IC for cryogenic infra-red sensors

Abstract

The paper proposes a low-cost scanning read-out IC architecture for large arrays of infra-red photon sensors operating at cryogenic temperatures. The low-power and compact 50/spl times/100 /spl mu/m/sup 2/ active pixel sensor area is achieved by the use of novel CMOS basic building blocks for single-capacitor integration and correlated double sampling, embedded pixel-test, pixel charge-multiplexing, video multiplexing and offset calibration. As a result, a low-cost 500/spl times/12 and 60 ns/pixel system-on-chip realization, capable of capturing high-resolution and real-time infra-red images, such as 640/spl times/500 @ 100 fps or 2560/spl times/500 @ 25 fps, is presented for a standard 0.35 /spl mu/m CMOS technology.