IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems最新文献

英文中文

Design of Compensator for Modified Multistage CIC-Based Decimation Filter with Improved Characteristics 改进特性的改进多级cic抽取滤波器补偿器设计

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2023-01-01 DOI: 10.1109/ISCAS46773.2023.10182010

G. Jovanovic-Dolecek

引用次数: 0

Using the Miller Theorem to Analyze Two-Stage Miller-Compensated Opamps 用米勒定理分析两阶段米勒补偿运算子

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2022-01-01 DOI: 10.1109/ISCAS48785.2022.9937345

R. S. A. Kumar

引用次数: 0

Analog processing by digital gates: fully synthesizable IC design for IoT interfaces 数字门模拟处理:物联网接口的完全可合成IC设计

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2020-01-01 DOI: 10.1109/ISCAS45731.2020.9180381

P. Crovetti, O. Aiello

引用次数: 0

A Parallel Radix-2 k FFT Processor using Single-Port Merged-Bank Memory 基于单端口合并存储的并行radix - 2k FFT处理器

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2019-05-26 DOI: 10.1109/ISCAS.2019.8702088

Wang Jian, Li Xianbin, Fan Guangteng, Tuo Zhouhui

This paper presents an area-efficient radix-2k FFT processor employing single-port memory, where the deployed memory is merged into 4 banks for arbitrary 2k-parallel computation. The proposed design enables the FFT input/output to operate in the parallelism equal to that of internal processing, and it paves the way for gaining high-throughput capability. Moreover, the in-place data caching strategy is available to allow the overlap between caching input data and supplying FFT results, which can further enhance throughput without consuming additional area. Theoretical and experimental comparisons demonstrate the proposed FFT processor can surpass the published related work in throughput while preserving high area efficiency.

本文提出了一种采用单端口存储器的面积高效的基数2k FFT处理器，其中部署的存储器合并为4组，用于任意2k并行计算。所提出的设计使FFT输入/输出以与内部处理相同的并行性运行，并为获得高吞吐量能力铺平了道路。此外，可以使用就地数据缓存策略来实现缓存输入数据和提供FFT结果之间的重叠，这可以在不消耗额外面积的情况下进一步提高吞吐量。理论和实验比较表明，所提出的FFT处理器在保持高面积效率的同时，吞吐量可以超过已发表的相关工作。

引用次数: 1

Differential Fowler-Nordheim Tunneling Dynamical System for Attojoule Sensing and Recording. 用于焦耳传感和记录的差分Fowler-Nordheim隧道动力系统。

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2019-05-01 DOI: 10.1109/iscas.2019.8702685

Darshit Mehta, Barani Raman, Shantanu Chakrabartty

Dynamical systems that evolve unidirectionally with respect to time provide a natural mechanism for implementing a time-domain, near-zero-threshold energy rectifier. In this paper we implement such a dynamical system using a pair of differential, leaky floating-gates and demonstrate that the circuit can sense and record signals of interest while compensating for environmental variations. A Fowler-Nordheim (FN) tunneling current has been used to implement the leakage process, which we experimentally show can be modulated by signals at energy levels below femtojoules. At this level of energy, the proposed FN-system could be self-powered using different types of biopotential energy sources like intra-cellular potentials, a feature that was not possible with previously reported recorders. Furthermore, the degree of modulation is shown to be a function of the input intensity as well as time-of-occurrence, which opens up the possibility of using reconstruction techniques to reconstruct the input signal from measurement of multiple sensing devices. Using devices fabricated in a 0.5 μm standard CMOS process, we demonstrate recording of 6 mV events with retention capability lasting over 30 minutes.

相对于时间单向演化的动力系统为实现时域、接近零阈值的能量整流器提供了一种自然机制。在本文中，我们使用一对差分漏动门实现了这样一个动态系统，并证明了该电路可以在补偿环境变化的同时感知和记录感兴趣的信号。Fowler-Nordheim (FN)隧穿电流用于实现泄漏过程，实验表明可以通过飞焦耳以下能级的信号进行调制。在这种能量水平上，所提出的fn系统可以使用不同类型的生物势能源(如细胞内电位)自供电，这是以前报道的记录仪无法实现的功能。此外，调制程度显示为输入强度和发生时间的函数，这开辟了使用重建技术从多个传感设备的测量中重建输入信号的可能性。利用0.5 μm标准CMOS工艺制造的器件，我们展示了6 mV事件的记录，保持能力持续超过30分钟。

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引用次数: 1

Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs fpga中嵌入式学习PCA实现的设计空间探索

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351540

Rodrigo Marino, J. M. Lanza-Gutiérrez, T. Riesgo, M. Holgado

Nowadays, the growth of Industry 4.0 and Internet of Things (IoT) demands new solutions for designing low-power low-cost advanced computational algorithms. This work develops the sensor signal processing layer of a chemical biosensing IoT edge device using NanoPillar transducers. We propose to move from smart sensors to expert sensors, applying Principal Component Analysis (PCA) for dimensionality reduction in FPGAs. As a result, this paper provides a design space exploration of PCA implementation over FPGAs, studying parameters as throughput and resource usage.

如今，工业4.0和物联网(IoT)的发展需要新的解决方案来设计低功耗、低成本的先进计算算法。本工作开发了使用纳米柱传感器的化学生物传感物联网边缘设备的传感器信号处理层。我们建议从智能传感器转向专家传感器，应用主成分分析(PCA)在fpga中进行降维。因此，本文提供了在fpga上实现PCA的设计空间探索，研究了吞吐量和资源使用等参数。

引用次数: 1

A Reconfigurable 28/56 Gb/s PAM4/NRZ Dual-mode SerDes with Hardware-reuse 一种可重构的28/ 56gb /s PAM4/NRZ双模服务器

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351612

Heng Liu, Li Ding, J. Jin, Jianjun J. Zhou

With the explosive growth of data rate demand, four-level pulse amplitude modulation (PAM4) SerDes standards are emerging, while binary non-return-to-zero (NRZ) standards still take the market. This paper proposes a novel dual-mode architecture designed for SerDes application data rate of up to 56 Gb/s with PAM4 modulation, and compatible to the legacy 28 Gb/s standards with NRZ modulation scheme. Attractively, with minor modification, the same hardware to send PAM4 signal can be used to implement a 28 Gb/s NRZ transmitter with 4-tap forward-feedback equalization (FFE), and meanwhile the PAM4 receiver can be easily reconfigured as a half-rate NRZ receiver with 1-tap loop-unrolled decision-feedback equalization (DFE). In addition, a digital duty-cycle correction (DCC) loop ensures the duty-cycle distortion (DCD) jitter introduced by half-rate transmitter architecture being less than 0.01UI in NRZ mode. The architecture is verified in 22nm CMOS FDSOI technology, and the simulation results across lossy channel show that the serial link transceiver can transmit 28/56 Gb/s with the eye opening of 400 mVpp in NRZ mode, and 150 mVpp in PAM4 mode in 1.2 V supply.

随着数据速率需求的爆炸式增长，四电平脉冲幅度调制(PAM4) SerDes标准正在兴起，而二元不归零(NRZ)标准仍然占据市场。本文提出了一种新的双模架构，设计用于SerDes应用，数据速率高达56 Gb/s，采用PAM4调制，兼容传统的28gb /s标准，采用NRZ调制方案。引人注目的是，只需稍加修改，发送PAM4信号的相同硬件就可以实现具有4分路前反馈均衡(FFE)的28 Gb/s NRZ发送器，同时PAM4接收器可以轻松地重新配置为具有1分路环卷决策反馈均衡(DFE)的半速率NRZ接收器。此外，数字占空比校正(DCC)环路确保了在NRZ模式下，由半速率发射机结构引入的占空比失真(DCD)抖动小于0.01UI。在22nm CMOS FDSOI技术上对该架构进行了验证，跨损耗信道的仿真结果表明，该串行链路收发器在1.2 V电源下，NRZ模式下的传输速率为400 mVpp, PAM4模式下的传输速率为150 mVpp，传输速率为28/56 Gb/s。

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引用次数: 1

Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators 开关电容CMFB对积分器全差分运算放大器增益的影响

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2018-05-27 DOI: 10.1109/ISCAS.2018.8351346

Joydeep Basu, P. Mandal

Switched capacitor common-mode feedback (SC-CMFB) is a popular technique for stabilization of the output common-mode level of fully differential operational amplifiers. It provides advantages of excellent linearity across a wide amplifier output swing, lowest power consumption, and better feedback loop stability in contrast to continuous CMFB; and hence, are suitable for realization of high-gain wide-swing low-power opamps. But, its implementation demands careful consideration of some practical aspects, a number of which are well documented in literature. However, its detrimental effect on the amplifier's differential-mode gain is not quite explored. Equivalent resistive loading from the SC-CMFB is the reason for this effect, and is particularly important in op-amps meant to have large gain (like, the folded cascode). This SC-CMFB induced drop in amplifier dc-gain, and the consequent effect on the design of continuous and discrete-time integrators have been discussed together with pertinent analytical derivations and transistor level simulations. A few practical guidelines and circuit topologies for minimizing the gain reduction effect have also been provided.

开关电容共模反馈(SC-CMFB)是一种稳定全差分运算放大器输出共模电平的常用技术。与连续CMFB相比，它具有在宽放大器输出摆幅范围内优异的线性度、最低的功耗和更好的反馈回路稳定性;因此，适用于实现高增益、宽摆幅、低功耗的运放大器。但是，它的实施需要仔细考虑一些实际方面，其中一些在文献中有很好的记录。然而，它对放大器的差模增益的不利影响并没有得到充分的探讨。SC-CMFB的等效电阻负载是产生这种效应的原因，在具有大增益的运放(如折叠级联码)中尤为重要。本文讨论了SC-CMFB引起的放大器直流增益下降及其对连续和离散时间积分器设计的影响，并给出了相关的解析推导和晶体管级仿真。还提供了一些实用的指南和电路拓扑结构，以尽量减少增益降低效应。

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引用次数: 6

High Linearity SAR ADC for Smart Sensor Applications 用于智能传感器应用的高线性SAR ADC

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2018-05-04 DOI: 10.1109/ISCAS.2018.8350998

Hua Fan, Jingxuan Yang, F. Maloberti, Q. Feng, Dagang Li, Daqian Hu, Yuanjun Cen, H. Heidari

This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor application. Monte Carlo simulation results show that capacitive array optimization technique proposed can make the SFDR, SNDR and (Signal-to-Noise Ratio) SNR more concentrated, which means the differences between maximum value and minimum value of SFDR, SNDR and SNR are much smaller than the conventional calibration techniques, more stable performance enhancement can be achieved, and the averaged SFDR is improved from 72.9 dB to 91.1 dB by using the capacitive array optimization method, 18.2 dB improvement of SFDR is obtained with only little expense of digital logic circuits, which makes it good choice for high resolution and high linearity smart sensing systems.

本文提出了一种电容阵列优化技术，用于提高连续逼近寄存器(SAR)模数转换器(ADC)的无杂散动态范围(SFDR)和信噪比(SNDR)。蒙特卡罗仿真结果表明，电容阵列优化技术可以使SFDR、SNDR和信噪比(信噪比)SNR更加集中，即SFDR、SNDR和SNR的最大值与最小值之差远小于常规校准技术，性能得到更稳定的增强，平均SFDR从72.9 dB提高到91.1 dB。在数字逻辑电路成本较低的情况下，SFDR提高18.2 dB，是高分辨率、高线性度智能传感系统的理想选择。

引用次数: 12

A Faster DiSH: Hardware Implementation of a Discrete Cell Signaling Network Simulator 一个更快的天线:一个离散小区信号网络模拟器的硬件实现

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

Pub Date : 2018-05-01 DOI: 10.1109/ISCAS.2018.8350960

Kevin Gilboy, Khaled Sayed, Niteesh Sundaram, Kara N. Bocan, Nataša Miškov-Živanov

Development of fast methods to conduct in silico experiments using computational models of cellular signaling is a promising approach toward advances in personalized medicine. However, software-based cellular network simulation has run-times plagued by wasted CPU cycles and unnecessary processes. Hardware-based simulation affords substantial speedup, but prior attempts at hardware-based biological simulation have been limited in scope and have suffered from inaccuracies due to poor random number generation. In this work, we propose several hardware-based simulation schemes utilizing novel random update index generation techniques for step-based and round-based stochastic simulations of cellular networks. Our results show improved runtimes while maintaining simulation accuracy compared to software implementations.

利用细胞信号的计算模型来进行计算机实验的快速方法的发展是个性化医疗进步的一个有前途的途径。然而，基于软件的蜂窝网络仿真在运行时受到CPU周期浪费和不必要进程的困扰。基于硬件的模拟提供了大量的加速，但之前基于硬件的生物模拟的尝试在范围上受到限制，并且由于随机数生成不良而存在不准确性。在这项工作中，我们提出了几种基于硬件的模拟方案，利用新颖的随机更新索引生成技术进行基于步骤和基于轮的蜂窝网络随机模拟。我们的结果表明，与软件实现相比，在保持仿真精度的同时，运行时间得到了改善。

引用次数: 2

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