Evaluating and comparing simulation verification vs. formal verification approach on block level design

Abstract

Logic design has become very complex in term of logic functionality. System-on-chip (SOC) designs are an integration of multiple modules and cores. In many cases, SOC integration is a result of integrating a few chips together. Each piece (module or core) must be verified separately (stand alone) prior to chip level verification. Standalone logic verification of the design is one of the most important steps in the overall design effort. Following the increase of the amount of functionality at each module, the logic verification effort has become a very resource-consuming task. Two logic verification methods are commonly used when verifying a SOC, simulation based verification and formal based verification. The two methods are explored and compared with respect to the time required for setup and running the environment, ease of debugging the reported failures, power, coverage and confidence level. Our main goal is to establish criteria for optimal use of simulation based verification and formal based verification and implement both methods on a block for a PCMCIA interface card. We have derived important conclusions concerning the matching of these methods for the verification of blocks of a similar type.