Detecting, locating and evaluating of partial discharges (PD) in the insulating material, terminations and joints provides the opportunity for a quality control after installation and preventive detection of arising service interruption. A sophisticated evaluation is necessary between PD in several insulating materials and also in different types of terminations and joints. For a most precise evaluation of the degree and risk caused by PD it is suggested to use a test voltage shape that is preferably like the same under service conditions. Only under these requirements the typical PD parameters like inception and extinction voltage, PD level and PD pattern correspond to significant operational values. On the other hand the stress on the insulation should be limited during the diagnosis to not create irreversible damages and thereby worsening the condition of the test object. The paper introduces an oscillating wave test system (OWTS), which meets these mentioned demands well. The design of the system, its functionality and especially the operating software are made for convenient field application. Field data and experience reports was presented and discussed. This field data serve also as good guide for the level of danger to the different insulating systems due to partial discharges.
{"title":"PD diagnosis on medium voltage cables with oscillating voltage (OWTS)","authors":"F. Petzold","doi":"10.1049/CP:20051119","DOIUrl":"https://doi.org/10.1049/CP:20051119","url":null,"abstract":"Detecting, locating and evaluating of partial discharges (PD) in the insulating material, terminations and joints provides the opportunity for a quality control after installation and preventive detection of arising service interruption. A sophisticated evaluation is necessary between PD in several insulating materials and also in different types of terminations and joints. For a most precise evaluation of the degree and risk caused by PD it is suggested to use a test voltage shape that is preferably like the same under service conditions. Only under these requirements the typical PD parameters like inception and extinction voltage, PD level and PD pattern correspond to significant operational values. On the other hand the stress on the insulation should be limited during the diagnosis to not create irreversible damages and thereby worsening the condition of the test object. The paper introduces an oscillating wave test system (OWTS), which meets these mentioned demands well. The design of the system, its functionality and especially the operating software are made for convenient field application. Field data and experience reports was presented and discussed. This field data serve also as good guide for the level of danger to the different insulating systems due to partial discharges.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89071248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399697
Yu Chen, A. Kahng, G. Robins, A. Zelikovsky, Yuhong Zheng
A new Open Artwork System Interchange Standard (OASIS) has recently been proposed to replace the GDSII (Graphic Design System II) format. A primary objective of the OASIS format is to enhance the compressibility of layout data. We compare the data compression capability of the full OASIS set of operators with those also present in GDSII, which we refer to as the restricted OASIS format. We measure the compression quality of the OASIS and GDSII operators in two contexts: (1) compressible fill generation, where the fill amounts are specified and compressible fill is then generated; (2) post-fill data compression, where the fill has already been generated and is then compressed. Our experimental results confirm the advantages of the OASIS compression operators: compressed file sizes using the full OASIS format are on average about twice as small as those obtained using the restricted OASIS format. We propose new OASIS-based compression algorithms which outperform industry physical verification tools. We also evaluate the respective merits of the individual repetition operators in OASIS, and suggest possible improvements to the OASIS repetition operators.
{"title":"Evaluation of the new OASIS format for layout fill compression","authors":"Yu Chen, A. Kahng, G. Robins, A. Zelikovsky, Yuhong Zheng","doi":"10.1109/ICECS.2004.1399697","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399697","url":null,"abstract":"A new Open Artwork System Interchange Standard (OASIS) has recently been proposed to replace the GDSII (Graphic Design System II) format. A primary objective of the OASIS format is to enhance the compressibility of layout data. We compare the data compression capability of the full OASIS set of operators with those also present in GDSII, which we refer to as the restricted OASIS format. We measure the compression quality of the OASIS and GDSII operators in two contexts: (1) compressible fill generation, where the fill amounts are specified and compressible fill is then generated; (2) post-fill data compression, where the fill has already been generated and is then compressed. Our experimental results confirm the advantages of the OASIS compression operators: compressed file sizes using the full OASIS format are on average about twice as small as those obtained using the restricted OASIS format. We propose new OASIS-based compression algorithms which outperform industry physical verification tools. We also evaluate the respective merits of the individual repetition operators in OASIS, and suggest possible improvements to the OASIS repetition operators.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75161335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399687
Amir Leshem, Youming Li
In this paper we study a simplified linear precoding scheme for FEXT cancellation in VDSL downstream transmission. We compare the proposed method to ideal zero forcing (ZF) FEXT cancellation and show that for multipair VDSL systems the method achieves rates that are close to the optimal theoretical rates without FEXT. We also derive a simple lower bound on the performance that allows us to predict the performance of the proposed algorithm. We end up with testing the proposed method on theoretical and empirical channels.
{"title":"A low complexity coordinated FEXT cancellation for VDSL","authors":"Amir Leshem, Youming Li","doi":"10.1109/ICECS.2004.1399687","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399687","url":null,"abstract":"In this paper we study a simplified linear precoding scheme for FEXT cancellation in VDSL downstream transmission. We compare the proposed method to ideal zero forcing (ZF) FEXT cancellation and show that for multipair VDSL systems the method achieves rates that are close to the optimal theoretical rates without FEXT. We also derive a simple lower bound on the performance that allows us to predict the performance of the proposed algorithm. We end up with testing the proposed method on theoretical and empirical channels.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74541851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399670
V. Potanin, E. E. Potanina
A watchdog comparator is presented that is tolerant of supply voltages significantly higher than the process limit for individual CMOS transistors. The circuit demonstrates very low current consumption, and has a fast dynamic response. The described circuit was implemented in the battery charger block of a power management IC for cellular phones. The implemented watchdog comparator is tolerant of input voltages up to 12 V and passes operational life and reliability tests. Extensive evaluation under various start-up conditions shows circuit compliance to contradictory specification parameters. Simulation and measurement data for various power-up transient conditions are presented.
{"title":"High-voltage tolerant watchdog comparator in a low-voltage CMOS technology","authors":"V. Potanin, E. E. Potanina","doi":"10.1109/ICECS.2004.1399670","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399670","url":null,"abstract":"A watchdog comparator is presented that is tolerant of supply voltages significantly higher than the process limit for individual CMOS transistors. The circuit demonstrates very low current consumption, and has a fast dynamic response. The described circuit was implemented in the battery charger block of a power management IC for cellular phones. The implemented watchdog comparator is tolerant of input voltages up to 12 V and passes operational life and reliability tests. Extensive evaluation under various start-up conditions shows circuit compliance to contradictory specification parameters. Simulation and measurement data for various power-up transient conditions are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77258809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399741
E. Margolis, Yonina C. Eldar
This paper introduces two new algorithms for perfect reconstruction of a periodic bandlimited signal from its nonuniform samples. We analyze the advantages and disadvantages of each method and discuss their properties. Based on the theory of frames, we also analyze the stability of the algorithms. Some special structures of the sampling points are investigated and we show that uniform sampling results in the most stable and simple reconstruction algorithm. We also provide experimental evidence to support our theoretical results.
{"title":"Reconstruction of nonuniformly sampled periodic signals: algorithms and stability analysis","authors":"E. Margolis, Yonina C. Eldar","doi":"10.1109/ICECS.2004.1399741","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399741","url":null,"abstract":"This paper introduces two new algorithms for perfect reconstruction of a periodic bandlimited signal from its nonuniform samples. We analyze the advantages and disadvantages of each method and discuss their properties. Based on the theory of frames, we also analyze the stability of the algorithms. Some special structures of the sampling points are investigated and we show that uniform sampling results in the most stable and simple reconstruction algorithm. We also provide experimental evidence to support our theoretical results.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75033975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399755
L. Liang, M. Ahmadi, M. Sid-Ahmed
In this paper, a genetic algorithm (GA) is used to design doubly complementary filter pairs, which are realized as a parallel connection of two all-pass filters. The designed filters have canonical signed-digit (CSD) coefficients. A new CSD number restoration technique is proposed to ensure that the algorithm generates CSD coefficients with the pre-specified wordlength and maximum number of non-zero digits.
{"title":"Design of complementary filter pairs with canonical signed-digit coefficients using genetic algorithm","authors":"L. Liang, M. Ahmadi, M. Sid-Ahmed","doi":"10.1109/ICECS.2004.1399755","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399755","url":null,"abstract":"In this paper, a genetic algorithm (GA) is used to design doubly complementary filter pairs, which are realized as a parallel connection of two all-pass filters. The designed filters have canonical signed-digit (CSD) coefficients. A new CSD number restoration technique is proposed to ensure that the algorithm generates CSD coefficients with the pre-specified wordlength and maximum number of non-zero digits.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80523828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399628
D. Akselrod, S. Greenberg, S. Hava
A multibit delta-sigma (/spl Delta//spl Sigma/) DAC employing enhanced noise-shaped dynamic element matching (DEM) architecture is presented. The architecture for implementing a noise-shaped DEM algorithm for use in multibit delta-sigma (/spl Delta//spl Sigma/) converters is analyzed. The suggested architecture shows the performance improvement as compared to previous solutions. System operation is discussed and hardware realization of the proposed architecture is described. A five-level /spl Delta//spl Sigma/ digital-to-analog (D/A) converter incorporating the proposed DEM architecture has been fabricated in a 0.12-/spl mu/m single-poly CMOS process. Finally, measured results are presented.
{"title":"Multibit /spl Delta//spl Sigma/ CMOS DAC employing enhanced noise-shaped DEM architecture","authors":"D. Akselrod, S. Greenberg, S. Hava","doi":"10.1109/ICECS.2004.1399628","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399628","url":null,"abstract":"A multibit delta-sigma (/spl Delta//spl Sigma/) DAC employing enhanced noise-shaped dynamic element matching (DEM) architecture is presented. The architecture for implementing a noise-shaped DEM algorithm for use in multibit delta-sigma (/spl Delta//spl Sigma/) converters is analyzed. The suggested architecture shows the performance improvement as compared to previous solutions. System operation is discussed and hardware realization of the proposed architecture is described. A five-level /spl Delta//spl Sigma/ digital-to-analog (D/A) converter incorporating the proposed DEM architecture has been fabricated in a 0.12-/spl mu/m single-poly CMOS process. Finally, measured results are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76629824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399729
I. Yarom, Gabi Glasser
Moore's law predicts that the number of transistors in a system will double every 18 months. However, in order to take advantage of the chip technology progress, the same progress needs to be made in the chip design process. The paper focuses on the benefit of SystemC technology in order to close this gap. We present research done in the Intel Development Center (IDC) with Tel-Aviv University (TAU) and Jerusalem College of Technology (JCT). The research explores different usages of SystemC in design and verification flow, which includes soft system verification (early in the design flows), architecture tradeoffs and a flow of SystemC to gate-level flow.
{"title":"SystemC opportunities in chip design flow","authors":"I. Yarom, Gabi Glasser","doi":"10.1109/ICECS.2004.1399729","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399729","url":null,"abstract":"Moore's law predicts that the number of transistors in a system will double every 18 months. However, in order to take advantage of the chip technology progress, the same progress needs to be made in the chip design process. The paper focuses on the benefit of SystemC technology in order to close this gap. We present research done in the Intel Development Center (IDC) with Tel-Aviv University (TAU) and Jerusalem College of Technology (JCT). The research explores different usages of SystemC in design and verification flow, which includes soft system verification (early in the design flows), architecture tradeoffs and a flow of SystemC to gate-level flow.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85460905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399765
H. Kfir, I. Kanter
In this paper, the belief propagation (BP) decoding of LDPC codes is extended to the case of joint source-channel coding. The uncompressed source is treated as a Markov process, characterized by a transition matrix, T, which is utilized as side information for the joint scheme. The method is based on the ability to calculate a prior for each decoded symbol separately, and re-estimate this prior dynamically after every iteration of the BP decoder. We demonstrate the implementation of this method using MacKay and Neel's LDPC algorithm over GF(q), and present simulation results indicating that the proposed scheme is competitive with the separate scheme, even when advanced compression algorithms (such as AC, PPM) are used. The extension to 2D (and higher) arrays of symbols is straight-forward. Finally, the ability of using the proposed scheme with the lack of side information is briefly sketched.
{"title":"Efficient LDPC codes for joint source-channel coding","authors":"H. Kfir, I. Kanter","doi":"10.1109/ICECS.2004.1399765","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399765","url":null,"abstract":"In this paper, the belief propagation (BP) decoding of LDPC codes is extended to the case of joint source-channel coding. The uncompressed source is treated as a Markov process, characterized by a transition matrix, T, which is utilized as side information for the joint scheme. The method is based on the ability to calculate a prior for each decoded symbol separately, and re-estimate this prior dynamically after every iteration of the BP decoder. We demonstrate the implementation of this method using MacKay and Neel's LDPC algorithm over GF(q), and present simulation results indicating that the proposed scheme is competitive with the separate scheme, even when advanced compression algorithms (such as AC, PPM) are used. The extension to 2D (and higher) arrays of symbols is straight-forward. Finally, the ability of using the proposed scheme with the lack of side information is briefly sketched.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78278697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-12-13DOI: 10.1109/ICECS.2004.1399756
D. Guermandi, E. Franchi, A. Gnudi
A design flow to explore the design parameters space of integrated inductively-degenerated low noise amplifiers (LNA), under the constraint of matched input impedance, is presented. It is based on standard circuit simulation tools and can be easily automated. The method is applied to the design of a 5.5 GHz 0.18 /spl mu/m CMOS LNA with minimum noise figure (NF) for a fixed bias current. The measured NF of 2.6 dB, with input reflection coefficient lower than -15 dB at 5 mA bias current, shows good agreement with simulations.
{"title":"A design flow for inductively degenerated LNAs","authors":"D. Guermandi, E. Franchi, A. Gnudi","doi":"10.1109/ICECS.2004.1399756","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399756","url":null,"abstract":"A design flow to explore the design parameters space of integrated inductively-degenerated low noise amplifiers (LNA), under the constraint of matched input impedance, is presented. It is based on standard circuit simulation tools and can be easily automated. The method is applied to the design of a 5.5 GHz 0.18 /spl mu/m CMOS LNA with minimum noise figure (NF) for a fixed bias current. The measured NF of 2.6 dB, with input reflection coefficient lower than -15 dB at 5 mA bias current, shows good agreement with simulations.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77425140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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