Pulse-width-modulation feedforward neural network design with on-chip learning

Abstract

In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under /spl plusmn/0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.