Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569292
J. Bor, Chung-Yu Wu
In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under /spl plusmn/0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.
{"title":"Pulse-width-modulation feedforward neural network design with on-chip learning","authors":"J. Bor, Chung-Yu Wu","doi":"10.1109/APCAS.1996.569292","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569292","url":null,"abstract":"In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under /spl plusmn/0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74083460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569246
Sang Jin Kim, H. Kang, H. Kim, Hee Kuck Oh, Y. Moon, Sung Han Park
This paper presents a desktop video conferencing system, called Seodang, for collaborative learning. Seodang enables individuals to participate in telelearning, connecting people together over distances in natural ways for the purpose of learning. The system consists of a video conferencing system and application-specific programs. The video conferencing system provides two-way audio and video communications using MuX. Other application programs include shared electronic whiteboard, query control system, presentation manager and student database manager. Each of these applications provides useful tools that improve the quality of learning, while students are allowed to participate interactively. Design and implementation of the system is presented along with its communication characteristics.
{"title":"Seodang: a desktop video conferencing system for collaborative learning","authors":"Sang Jin Kim, H. Kang, H. Kim, Hee Kuck Oh, Y. Moon, Sung Han Park","doi":"10.1109/APCAS.1996.569246","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569246","url":null,"abstract":"This paper presents a desktop video conferencing system, called Seodang, for collaborative learning. Seodang enables individuals to participate in telelearning, connecting people together over distances in natural ways for the purpose of learning. The system consists of a video conferencing system and application-specific programs. The video conferencing system provides two-way audio and video communications using MuX. Other application programs include shared electronic whiteboard, query control system, presentation manager and student database manager. Each of these applications provides useful tools that improve the quality of learning, while students are allowed to participate interactively. Design and implementation of the system is presented along with its communication characteristics.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75754699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569325
Woojung Lee, Jae-Ho Chung
In this paper, a fingerprint recognition algorithm is suggested. The algorithm is developed based on the wavelet transform, the dominant local orientation (DLO) and coherence that derived from the gradient of Gaussian. Computer simulation results show that while the rate of Type II error Incorrect recognition of two different fingerprints as identical fingerprints-is held at 0.0%, the rate of Type I error-Incorrect recognition of two identical fingerprints as different ones-is 2.5%.
{"title":"Automatic real-time identification of fingerprint images using wavelet transform and gradient of Gaussian","authors":"Woojung Lee, Jae-Ho Chung","doi":"10.1109/APCAS.1996.569325","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569325","url":null,"abstract":"In this paper, a fingerprint recognition algorithm is suggested. The algorithm is developed based on the wavelet transform, the dominant local orientation (DLO) and coherence that derived from the gradient of Gaussian. Computer simulation results show that while the rate of Type II error Incorrect recognition of two different fingerprints as identical fingerprints-is held at 0.0%, the rate of Type I error-Incorrect recognition of two identical fingerprints as different ones-is 2.5%.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79029220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569304
L. Sellami, Kuan Wong, R. W. Newcomb
Hair cells act as neural interfaces of sound signals and, therefore, circuit representations are important to signal processing systems based upon characteristics of the ear. Here a nonlinear bidirectional model of a hair-cell is presented. Also developed are a canonical semi-state description for its Potassium and Sodium channels, and circuits suitable for a transistorized hardware implementation.
{"title":"Semi-state description of potassium and sodium channels in hair-cell-type circuits","authors":"L. Sellami, Kuan Wong, R. W. Newcomb","doi":"10.1109/APCAS.1996.569304","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569304","url":null,"abstract":"Hair cells act as neural interfaces of sound signals and, therefore, circuit representations are important to signal processing systems based upon characteristics of the ear. Here a nonlinear bidirectional model of a hair-cell is presented. Also developed are a canonical semi-state description for its Potassium and Sodium channels, and circuits suitable for a transistorized hardware implementation.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84221796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569280
Young-Keun Park, Gyungho Lee
Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue in the switch design. In this paper, we propose a practically implementable large scale ATM switch by, integrating time-division and space-division switch architectures. We present a scalable shared buffer type switch and its expansion method.
{"title":"A modular and scalable ATM switch using shared buffer architecture","authors":"Young-Keun Park, Gyungho Lee","doi":"10.1109/APCAS.1996.569280","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569280","url":null,"abstract":"Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue in the switch design. In this paper, we propose a practically implementable large scale ATM switch by, integrating time-division and space-division switch architectures. We present a scalable shared buffer type switch and its expansion method.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85621832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569206
Mi-Sook Chung, S. Kang, Jae-Ho Choi, Hoon-Sung Kwak
In this paper, we propose a new multiresolution motion estimation (NMRME) scheme for wavelet transform based video coding to increase the PSNR. In the NMRME scheme, motion vectors are estimated for low pass subimages of every layers, and all component subimages at the lowest layer by the block matching. At first the motion vectors are calculated for the low pass subimage at highest layer. Then, motion vectors at lower layers are refined using the motion information obtained at higher layers. Motion vectors for vertical, horizontal, and diagonal component subimages at lowest layers are refined using the motion vectors obtained at the low pass subimage of the same layer. Considering the simulation result, the PSNR is higher in the NMRME than that in MRME and FMRME. But, the bit rate is higher. Therefore, tile NMRME scheme is adequate for the application which requires a high PSNR.
{"title":"New multiresolution motion estimation for wavelet transform video coding","authors":"Mi-Sook Chung, S. Kang, Jae-Ho Choi, Hoon-Sung Kwak","doi":"10.1109/APCAS.1996.569206","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569206","url":null,"abstract":"In this paper, we propose a new multiresolution motion estimation (NMRME) scheme for wavelet transform based video coding to increase the PSNR. In the NMRME scheme, motion vectors are estimated for low pass subimages of every layers, and all component subimages at the lowest layer by the block matching. At first the motion vectors are calculated for the low pass subimage at highest layer. Then, motion vectors at lower layers are refined using the motion information obtained at higher layers. Motion vectors for vertical, horizontal, and diagonal component subimages at lowest layers are refined using the motion vectors obtained at the low pass subimage of the same layer. Considering the simulation result, the PSNR is higher in the NMRME than that in MRME and FMRME. But, the bit rate is higher. Therefore, tile NMRME scheme is adequate for the application which requires a high PSNR.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77152378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569319
Mao-Fu Lai, C. Hsieh
This paper presents a novel VLSI architecture for the squared-error clustering algorithm. The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PEs, and it is modular, regular, and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture.
{"title":"A novel VLSI architecture for clustering analysis","authors":"Mao-Fu Lai, C. Hsieh","doi":"10.1109/APCAS.1996.569319","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569319","url":null,"abstract":"This paper presents a novel VLSI architecture for the squared-error clustering algorithm. The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PEs, and it is modular, regular, and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80992276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569244
Seon-Ja Kim, Young-Duk Park
With the advance of multimedia and network technology, it is possible to integrate telecommunication, broadcasting, and information processing services as a new interactive multimedia service. However, the current service has problems of incompatibilities between service systems and proprietary standard based services. To solve these problems, DAVIC (Digital Audio-Visual Council) is establishing standardization of interactive multimedia services. We have designed and implemented an interactive multimedia service system based on the DAVIC specification. In this paper, we describe the overall system architecture of our approach and implementation results.
{"title":"Implementation of interactive multimedia service system","authors":"Seon-Ja Kim, Young-Duk Park","doi":"10.1109/APCAS.1996.569244","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569244","url":null,"abstract":"With the advance of multimedia and network technology, it is possible to integrate telecommunication, broadcasting, and information processing services as a new interactive multimedia service. However, the current service has problems of incompatibilities between service systems and proprietary standard based services. To solve these problems, DAVIC (Digital Audio-Visual Council) is establishing standardization of interactive multimedia services. We have designed and implemented an interactive multimedia service system based on the DAVIC specification. In this paper, we describe the overall system architecture of our approach and implementation results.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81158198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569295
S. Wakabayashi, Y. Kishimoto, T. Koide
In this paper, we propose an optimal pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density by assigning nets to terminals of cells. If the number of possible terminal assignments for each cell is bounded by some constant r, then the proposed algorithm runs in linear time. In most practical cases, the value of r is relatively small, and thus the proposed algorithm is effective and efficient to reduce the chip area.
{"title":"An optimal pin assignment algorithm with improvement of cell placement in standard cell layout","authors":"S. Wakabayashi, Y. Kishimoto, T. Koide","doi":"10.1109/APCAS.1996.569295","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569295","url":null,"abstract":"In this paper, we propose an optimal pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density by assigning nets to terminals of cells. If the number of possible terminal assignments for each cell is bounded by some constant r, then the proposed algorithm runs in linear time. In most practical cases, the value of r is relatively small, and thus the proposed algorithm is effective and efficient to reduce the chip area.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84162303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-18DOI: 10.1109/APCAS.1996.569300
A.J. Correia, J. Guilherme, J. Franca
Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.
{"title":"Current-mode algorithmic pipeline analog-to-digital converter","authors":"A.J. Correia, J. Guilherme, J. Franca","doi":"10.1109/APCAS.1996.569300","DOIUrl":"https://doi.org/10.1109/APCAS.1996.569300","url":null,"abstract":"Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81323739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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