{"title":"Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs","authors":"S. Kazeminia, A. Soltani","doi":"10.1109/APCCAS.2016.7804064","DOIUrl":null,"url":null,"abstract":"A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers (RAs). Two identical RAs are concurrently used which are in turn corrected for absolute gain value. Although the main RA is disconnected from data path for calibration, however, is replaced by a corrected one and resolves discontinuous conversion in regular foreground methods. A digitally assisted interface, includes inc/dec ACC and DAC, is utilized to store the loop results, even if RA leaves the correction loop. Monte-Carlo analysis for 100 iterations at all corner conditions shows that the correction loop provides ideal gain of 4 with median value of 3.996 and standard deviation of 0.003, while threshold voltages and reference levels experience 25mVolts variations at 3σ in Gaussian distribution. Linearity, drops to 9-bit for 50mVolts peak-to-peak variations on residue. Simulations are performed using the BSIM3v3 model of a 0.18μm CMOS technology.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"680-683"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7804064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers (RAs). Two identical RAs are concurrently used which are in turn corrected for absolute gain value. Although the main RA is disconnected from data path for calibration, however, is replaced by a corrected one and resolves discontinuous conversion in regular foreground methods. A digitally assisted interface, includes inc/dec ACC and DAC, is utilized to store the loop results, even if RA leaves the correction loop. Monte-Carlo analysis for 100 iterations at all corner conditions shows that the correction loop provides ideal gain of 4 with median value of 3.996 and standard deviation of 0.003, while threshold voltages and reference levels experience 25mVolts variations at 3σ in Gaussian distribution. Linearity, drops to 9-bit for 50mVolts peak-to-peak variations on residue. Simulations are performed using the BSIM3v3 model of a 0.18μm CMOS technology.