Pub Date : 2020-01-01DOI: 10.1109/apccas50809.2020.9301647
R. Liu
{"title":"IoT and Blockchain: Technologies, Challenges, and Applications","authors":"R. Liu","doi":"10.1109/apccas50809.2020.9301647","DOIUrl":"https://doi.org/10.1109/apccas50809.2020.9301647","url":null,"abstract":"","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"47 1","pages":"i"},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79713651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA implementation of edge detection for Sobel operator in eight directions","authors":"Xiangxi Zou, Yonghui Zhang, Shuaiyan Zhang, Jian Zhang","doi":"10.1109/APCCAS.2018.8605703","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605703","url":null,"abstract":"","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"41 1","pages":"520-523"},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79239055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-01DOI: 10.1109/APCCAS.2018.8605673
Kuojun Yang, P. Ye, Duyu Qiu, Jiali Shi
{"title":"Teaching Practice Platform and Innovation Course Construction for Postgraduate Majoring in Electronics Information","authors":"Kuojun Yang, P. Ye, Duyu Qiu, Jiali Shi","doi":"10.1109/APCCAS.2018.8605673","DOIUrl":"https://doi.org/10.1109/APCCAS.2018.8605673","url":null,"abstract":"","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"168 1","pages":"354-357"},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78070720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-28DOI: 10.1109/APCCAS.2016.7803902
Douglas Andersson Hagglund, G. A. Subbarao, Mohammed Abdulaziz, Markus Törmänen
In this paper we present an audio synthesizer that creates audio signals, intended to be reproduced as sound by a loudspeaker. This paper details the design, implementation and verification of an analog, subtractive audio synthesizer. The synthesizer produces a variety of waveforms spanning approximately 3 octaves. The frequency is controlled by an external voltage and the harmonic content is regulated by a tunable filter. The system is fabricated in 130 nm CMOS. Current consumption measures between 1.8 and 2.1 mA from a supply of 1.2 V.
{"title":"Analog integrated audio frequency synthesizer","authors":"Douglas Andersson Hagglund, G. A. Subbarao, Mohammed Abdulaziz, Markus Törmänen","doi":"10.1109/APCCAS.2016.7803902","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803902","url":null,"abstract":"In this paper we present an audio synthesizer that creates audio signals, intended to be reproduced as sound by a loudspeaker. This paper details the design, implementation and verification of an analog, subtractive audio synthesizer. The synthesizer produces a variety of waveforms spanning approximately 3 octaves. The frequency is controlled by an external voltage and the harmonic content is regulated by a tunable filter. The system is fabricated in 130 nm CMOS. Current consumption measures between 1.8 and 2.1 mA from a supply of 1.2 V.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"26 1","pages":"83-86"},"PeriodicalIF":0.0,"publicationDate":"2016-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78781266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803928
Hao-Fan Hsu, Chia-Wei Chang, Chih-Peng Fan
In this work, fast algorithm-based multiple transforms with a hardware-sharing design are exploited for 4×4 and 8×8 forward transforms in H.264/AVC, VC-1, HEVC, and AVS standards, and for 8×8 forward transforms in MPEG-1/2/4 schemes. The 4×4 VP8 and AVS-M fast forward transforms are developed by cost-sharing hardware for multi-standard video encoding applications. By matrix factorizations, our proposed 1D hardware-sharing transform architecture is realized by only shifters and adders. Compared with the directly combined fast algorithms without hardware-sharing functionality, our proposed architecture reduces the number of shifters and adders by 24.5% and 73.4%, respectively. Compared with existing multi-standard transform designs, our proposed architecture reveals larger normalized hardware efficiency. Our proposed hardware sharing based 1-D forward transform supports the Full HD (1920×1080@60Hz) specification with the 110.8MHz working frequency.
{"title":"High-efficiency and cost-sharing architecture design of fast algorithm based multiple 4×4 and 8×8 forward transforms for multi-standard video encoder","authors":"Hao-Fan Hsu, Chia-Wei Chang, Chih-Peng Fan","doi":"10.1109/APCCAS.2016.7803928","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803928","url":null,"abstract":"In this work, fast algorithm-based multiple transforms with a hardware-sharing design are exploited for 4×4 and 8×8 forward transforms in H.264/AVC, VC-1, HEVC, and AVS standards, and for 8×8 forward transforms in MPEG-1/2/4 schemes. The 4×4 VP8 and AVS-M fast forward transforms are developed by cost-sharing hardware for multi-standard video encoding applications. By matrix factorizations, our proposed 1D hardware-sharing transform architecture is realized by only shifters and adders. Compared with the directly combined fast algorithms without hardware-sharing functionality, our proposed architecture reduces the number of shifters and adders by 24.5% and 73.4%, respectively. Compared with existing multi-standard transform designs, our proposed architecture reveals larger normalized hardware efficiency. Our proposed hardware sharing based 1-D forward transform supports the Full HD (1920×1080@60Hz) specification with the 110.8MHz working frequency.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"66 1","pages":"184-187"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73908727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804064
S. Kazeminia, A. Soltani
A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers (RAs). Two identical RAs are concurrently used which are in turn corrected for absolute gain value. Although the main RA is disconnected from data path for calibration, however, is replaced by a corrected one and resolves discontinuous conversion in regular foreground methods. A digitally assisted interface, includes inc/dec ACC and DAC, is utilized to store the loop results, even if RA leaves the correction loop. Monte-Carlo analysis for 100 iterations at all corner conditions shows that the correction loop provides ideal gain of 4 with median value of 3.996 and standard deviation of 0.003, while threshold voltages and reference levels experience 25mVolts variations at 3σ in Gaussian distribution. Linearity, drops to 9-bit for 50mVolts peak-to-peak variations on residue. Simulations are performed using the BSIM3v3 model of a 0.18μm CMOS technology.
{"title":"Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs","authors":"S. Kazeminia, A. Soltani","doi":"10.1109/APCCAS.2016.7804064","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804064","url":null,"abstract":"A digitally-assisted foreground-liked gain calibration mechanism is proposed for open loop residue amplifiers (RAs). Two identical RAs are concurrently used which are in turn corrected for absolute gain value. Although the main RA is disconnected from data path for calibration, however, is replaced by a corrected one and resolves discontinuous conversion in regular foreground methods. A digitally assisted interface, includes inc/dec ACC and DAC, is utilized to store the loop results, even if RA leaves the correction loop. Monte-Carlo analysis for 100 iterations at all corner conditions shows that the correction loop provides ideal gain of 4 with median value of 3.996 and standard deviation of 0.003, while threshold voltages and reference levels experience 25mVolts variations at 3σ in Gaussian distribution. Linearity, drops to 9-bit for 50mVolts peak-to-peak variations on residue. Simulations are performed using the BSIM3v3 model of a 0.18μm CMOS technology.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"1 1","pages":"680-683"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74299068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803920
Kai Yang, M. Sheu
In this paper, we propose an image target tracking algorithm for an embedded platform. Our proposed can process 1280 × 720 resolution video sequences and provide accurate image tracking in real time. In the tracking algorithm, an adaptive local edge detection method is employed to extract the feature pixels of a tracked object. To reduce tracking errors, a region-based local binary pattern feature method was employed to describe the edge pixels of the tracked object. Finally, we implemented this object tracking method in the embedded platform to achieve real-time execution for experimental testing in a complex environment.
{"title":"Edge-based moving object tracking algorithm for an embedded system","authors":"Kai Yang, M. Sheu","doi":"10.1109/APCCAS.2016.7803920","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803920","url":null,"abstract":"In this paper, we propose an image target tracking algorithm for an embedded platform. Our proposed can process 1280 × 720 resolution video sequences and provide accurate image tracking in real time. In the tracking algorithm, an adaptive local edge detection method is employed to extract the feature pixels of a tracked object. To reduce tracking errors, a region-based local binary pattern feature method was employed to describe the edge pixels of the tracked object. Finally, we implemented this object tracking method in the embedded platform to achieve real-time execution for experimental testing in a complex environment.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"39 1","pages":"153-155"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74926957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803960
Xiuqin Wei, H. Sekiya, T. Suetsugu
This paper presents a novel circuit topology of the class-E rectifier by introducing the concept of the class-F rectifier into the basic class-E rectifier. In the proposed class-E rectifier, a harmonic component is added to the switching device of the basic class-E rectifier. Therefore, the proposed class-E rectifier possesses the strengths of both the class-E and -F rectifiers, enabling simple configuration, low peak switch voltage, and high efficiency. A design example is given along with the PSpice-simulation waveforms. The switch voltage and current waveforms from the PSpice simulation satisfy the zero-voltage and zero-current soft switching conditions, namely, the switch voltage and current reach zero in the turn off and on instants, respectively. Therefore, the proposed class-E rectifier can achieve high power-conversion efficiency at high frequencies. Additionally, the peak switch voltage is reduced significantly compared with the basic class-E rectifier but the circuit configuration is as simple as the basic class-E rectifier. It is seen from the PSpise-simulation results that the numerical calculations agreed with the simulated ones quantitatively, which validated the accuracy and effectiveness of the proposed rectifier.
{"title":"New class-E rectifier with low voltage stress","authors":"Xiuqin Wei, H. Sekiya, T. Suetsugu","doi":"10.1109/APCCAS.2016.7803960","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803960","url":null,"abstract":"This paper presents a novel circuit topology of the class-E rectifier by introducing the concept of the class-F rectifier into the basic class-E rectifier. In the proposed class-E rectifier, a harmonic component is added to the switching device of the basic class-E rectifier. Therefore, the proposed class-E rectifier possesses the strengths of both the class-E and -F rectifiers, enabling simple configuration, low peak switch voltage, and high efficiency. A design example is given along with the PSpice-simulation waveforms. The switch voltage and current waveforms from the PSpice simulation satisfy the zero-voltage and zero-current soft switching conditions, namely, the switch voltage and current reach zero in the turn off and on instants, respectively. Therefore, the proposed class-E rectifier can achieve high power-conversion efficiency at high frequencies. Additionally, the peak switch voltage is reduced significantly compared with the basic class-E rectifier but the circuit configuration is as simple as the basic class-E rectifier. It is seen from the PSpise-simulation results that the numerical calculations agreed with the simulated ones quantitatively, which validated the accuracy and effectiveness of the proposed rectifier.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"21 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73217914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803909
K. Hafeez, A. Dutta, S. Singh, Krishna Kanth Gowri Avalur
This paper proposes on-chip soft-start method with minimum extra components and turbulence free start up of dc-dc converter. During the soft start, the output voltage is slowly increased to the steady state value so that the inrush current and overshoots are prevented. The proposed topology is implemented in buck converter designed to give 3.3V output for wide supply range of 4.5V to 18V and load range of 0 to 3A in AMS 0.35μm high-voltage CMOS process. Experimental results show that the novel on-chip soft-start circuit is able to reach to steady state voltage without massive inrush current and overshoot in 36 us of time.
{"title":"A compact, resource sharing on-chip soft-start technique for automotive DC-DC converters","authors":"K. Hafeez, A. Dutta, S. Singh, Krishna Kanth Gowri Avalur","doi":"10.1109/APCCAS.2016.7803909","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803909","url":null,"abstract":"This paper proposes on-chip soft-start method with minimum extra components and turbulence free start up of dc-dc converter. During the soft start, the output voltage is slowly increased to the steady state value so that the inrush current and overshoots are prevented. The proposed topology is implemented in buck converter designed to give 3.3V output for wide supply range of 4.5V to 18V and load range of 0 to 3A in AMS 0.35μm high-voltage CMOS process. Experimental results show that the novel on-chip soft-start circuit is able to reach to steady state voltage without massive inrush current and overshoot in 36 us of time.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"87 1","pages":"111-114"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74103710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803911
Karim Ali, Fei Li, S. Lua, C. Heng
This paper proposes a compact spin transfer torque non-volatile flip-flop (STT-NVFF) design. The proposed NVFF adds four transistors and two complementary magnetic tunnel junctions (MTJs) over a standard volatile flip-flop with only 18% area overhead. The NVFF utilizes a low power/ fast switching MTJ that permits the elimination of the write circuitry existing in conventional STT-NVFFs. The proposed NVFF is at least 80% smaller area than conventional STT-NVFFs that uses write circuitry with, at least, the same energy efficiency. It achieves a low backup energy of 111 fJ and restore energy of 6.9 fJ within 3 ns and 0.16 ns respectively. Moreover, it realizes a 72% reduction in break-even point (BEP) and a 10% area reduction compared to an STT-NVFF employing the latch as a writer.
{"title":"Compact spin transfer torque non-volatile flip flop design for power-gating architecture","authors":"Karim Ali, Fei Li, S. Lua, C. Heng","doi":"10.1109/APCCAS.2016.7803911","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803911","url":null,"abstract":"This paper proposes a compact spin transfer torque non-volatile flip-flop (STT-NVFF) design. The proposed NVFF adds four transistors and two complementary magnetic tunnel junctions (MTJs) over a standard volatile flip-flop with only 18% area overhead. The NVFF utilizes a low power/ fast switching MTJ that permits the elimination of the write circuitry existing in conventional STT-NVFFs. The proposed NVFF is at least 80% smaller area than conventional STT-NVFFs that uses write circuitry with, at least, the same energy efficiency. It achieves a low backup energy of 111 fJ and restore energy of 6.9 fJ within 3 ns and 0.16 ns respectively. Moreover, it realizes a 72% reduction in break-even point (BEP) and a 10% area reduction compared to an STT-NVFF employing the latch as a writer.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"67 1","pages":"119-122"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74325968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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