Stepped Doped High k VDMOS: Switching Characteristics

Abstract

This paper presents the switching analysis of vertical stepped doped high k VDMOS. The introduction of vertical step doping in the n pillar of HK VDMOS brings improvement in switching performance. All the analysis of proposed and conventional device is carried out using silvaco ATLAS tool. Significant reduction in the switching delay is noted for different values of k. It is observed to be 40% for k = 20, 28.57% for k = 10, and 31.76% for k = 5. So the proposed step doped high k VDMOS can replace the high k VDMOS when fast switching is desired.