Cyclic Scheduling of Loop-Intensive Applications on Heterogeneous Multiprocessor Architectures

Abstract

This paper tackles the scheduling of loop-intensive applications modeled by synchronous dataflow graphs (SDFGs) on heterogeneous multiprocessor architectures under resource and communication constraints. Scheduling an application graph on multiprocessor architectures under resource constraints is a well-known NP-hard problem widely addressed in the previous decades with the goal of optimizing different performance metrics such as latency, memory allocations, energy consumption, throughput, etc. In this paper, we focus on the study of cyclic scheduling strategies and specifically the software pipelined schedules of SDFGs under the resource and communication constraints of heterogeneous multiprocessor architectures and we made two major contributions. The first contribution is an integer linear programming (ILP) model for the exact resolution of the scheduling problem and the second contribution is a time-efficient heuristic that generates scheduling solutions close to the optimal solutions generated with our ILP model.