Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00016
Benjamin Binder, Mihail Asavoae, F. Brandner, Belgacem Ben Hedia, M. Jan
Intuitively, a counter-intuitive timing anomaly manifests when a locally faster execution becomes globally slower. While the presence of such timing anomalies threatens the soundness and/or scalability of timing analyses, tools to systematically detect them do not exist. The main reason lies in the absence of a definition of counter-intuitive timing anomalies that establishes relations between local and global timing effects. In this paper, we address these relations through an important concept, that of causality, which we further use to revise the formalization of counter-intuitive timing anomalies. We also propose a specialized instance of the notions to implement a detection procedure for out-of-order pipelines.
{"title":"The Role of Causality in a Formal Definition of Timing Anomalies","authors":"Benjamin Binder, Mihail Asavoae, F. Brandner, Belgacem Ben Hedia, M. Jan","doi":"10.1109/RTCSA55878.2022.00016","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00016","url":null,"abstract":"Intuitively, a counter-intuitive timing anomaly manifests when a locally faster execution becomes globally slower. While the presence of such timing anomalies threatens the soundness and/or scalability of timing analyses, tools to systematically detect them do not exist. The main reason lies in the absence of a definition of counter-intuitive timing anomalies that establishes relations between local and global timing effects. In this paper, we address these relations through an important concept, that of causality, which we further use to revise the formalization of counter-intuitive timing anomalies. We also propose a specialized instance of the notions to implement a detection procedure for out-of-order pipelines.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"44 1","pages":"91-102"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73503594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00014
Dawei Shen, Tianyu Zhang, Jiachen Wang, Qingxu Deng, Song Han, X. Hu
With the rapid growth of industrial Internet of Things (IIoT) applications, real-time wireless networks (RTWNs) are playing an increasingly important role in providing realtime, reliable, and secure communication services for these applications. A key challenge in RTWN management is to ensure real-time Quality of Services (QoS), especially in the presence of unexpected external (i.e., application-side) and internal (i.e., network-side) disturbances. This paper presents a novel framework, DS-PaS, to determine the packet transmission schedule for multi-channel multi-hop RTWNs at the data link layer in a distributed and dynamic fashion. DS-PaS is able to (i) handle external disturbances, (ii) support spatial reuse, (iii) meet deadlines of all critical tasks, and (iv) minimize the number of dropped non-critical packets. To avoid transmission collisions when using inconsistent information in a distributed framework, DS-PaS incorporates several key advances in both the data-link layer protocol and algorithm design so that individual nodes can build on-line schedules with only local interference information. Extensive evaluation based on both testbed implementation and simulation validates the correctness of the DS-PaS design and demonstrates its effectiveness compared to the state of the art.
{"title":"Distributed Successive Packet Scheduling for Multi-Channel Real-Time Wireless Networks","authors":"Dawei Shen, Tianyu Zhang, Jiachen Wang, Qingxu Deng, Song Han, X. Hu","doi":"10.1109/RTCSA55878.2022.00014","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00014","url":null,"abstract":"With the rapid growth of industrial Internet of Things (IIoT) applications, real-time wireless networks (RTWNs) are playing an increasingly important role in providing realtime, reliable, and secure communication services for these applications. A key challenge in RTWN management is to ensure real-time Quality of Services (QoS), especially in the presence of unexpected external (i.e., application-side) and internal (i.e., network-side) disturbances. This paper presents a novel framework, DS-PaS, to determine the packet transmission schedule for multi-channel multi-hop RTWNs at the data link layer in a distributed and dynamic fashion. DS-PaS is able to (i) handle external disturbances, (ii) support spatial reuse, (iii) meet deadlines of all critical tasks, and (iv) minimize the number of dropped non-critical packets. To avoid transmission collisions when using inconsistent information in a distributed framework, DS-PaS incorporates several key advances in both the data-link layer protocol and algorithm design so that individual nodes can build on-line schedules with only local interference information. Extensive evaluation based on both testbed implementation and simulation validates the correctness of the DS-PaS design and demonstrates its effectiveness compared to the state of the art.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1 1","pages":"71-80"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83679548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00019
M. Bechtel, QiTao Weng, H. Yun
Running deep neural networks (DNNs) on tiny Micro-controller Units (MCUs) is challenging due to their limitations in computing, memory, and storage capacity. Fortunately, recent advances in both MCU hardware and machine learning software frameworks make it possible to run fairly complex neural networks on modern MCUs, resulting in a new field of study widely known as TinyML. However, there have been few studies to show the potential for TinyML applications in cyber physical systems (CPS).In this paper, we present DeepPicarMicro, a small self-driving RC car testbed, which runs a convolutional neural network (CNN) on a Raspberry Pi Pico MCU. We apply a state-of-the-art DNN optimization to successfully fit the well-known PilotNet CNN architecture, which was used to drive NVIDIA’s real self-driving car, on the MCU. We apply a state-of-art network architecture search (NAS) approach to find further optimized networks that can effectively control the car in real-time in an end-to-end manner. From an extensive systematic experimental evaluation study, we observe an interesting relationship between the accuracy, latency, and control performance of a system. From this, we propose a joint optimization strategy that takes both accuracy and latency of a model in the network architecture search process for AI enabled CPS.
{"title":"DeepPicarMicro: Applying TinyML to Autonomous Cyber Physical Systems","authors":"M. Bechtel, QiTao Weng, H. Yun","doi":"10.1109/RTCSA55878.2022.00019","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00019","url":null,"abstract":"Running deep neural networks (DNNs) on tiny Micro-controller Units (MCUs) is challenging due to their limitations in computing, memory, and storage capacity. Fortunately, recent advances in both MCU hardware and machine learning software frameworks make it possible to run fairly complex neural networks on modern MCUs, resulting in a new field of study widely known as TinyML. However, there have been few studies to show the potential for TinyML applications in cyber physical systems (CPS).In this paper, we present DeepPicarMicro, a small self-driving RC car testbed, which runs a convolutional neural network (CNN) on a Raspberry Pi Pico MCU. We apply a state-of-the-art DNN optimization to successfully fit the well-known PilotNet CNN architecture, which was used to drive NVIDIA’s real self-driving car, on the MCU. We apply a state-of-art network architecture search (NAS) approach to find further optimized networks that can effectively control the car in real-time in an end-to-end manner. From an extensive systematic experimental evaluation study, we observe an interesting relationship between the accuracy, latency, and control performance of a system. From this, we propose a joint optimization strategy that takes both accuracy and latency of a model in the network architecture search process for AI enabled CPS.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"46 1","pages":"120-127"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87832510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00013
Abdulrahman Bukhari, Seyedmehdi Hosseinimotlagh, Hyoseung Kim
The rapid advancement of IoT technologies has generated much interest in the development of learning-based sensing applications on embedded edge devices. However, these efforts are being challenged by the need to adapt to unforeseen conditions in an open-world environment. Updating a learning model suffers from the lack of training data as well as the high computational demand beyond that available on edge devices. In this paper, we propose an open-world time-series sensing framework for making inferences from time-series sensor data and achieving incremental learning on an embedded edge device with limited resources. The proposed framework is able to achieve two essential tasks, inference and learning, without requiring access to a powerful cloud server. We discuss the design choices made to ensure satisfactory learning performance and efficient resource usage. Experimental results demonstrate the ability of the system to incrementally adapt to unforeseen conditions and to effectively run on a resource-constrained device.
{"title":"An Open-World Time-Series Sensing Framework for Embedded Edge Devices","authors":"Abdulrahman Bukhari, Seyedmehdi Hosseinimotlagh, Hyoseung Kim","doi":"10.1109/RTCSA55878.2022.00013","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00013","url":null,"abstract":"The rapid advancement of IoT technologies has generated much interest in the development of learning-based sensing applications on embedded edge devices. However, these efforts are being challenged by the need to adapt to unforeseen conditions in an open-world environment. Updating a learning model suffers from the lack of training data as well as the high computational demand beyond that available on edge devices. In this paper, we propose an open-world time-series sensing framework for making inferences from time-series sensor data and achieving incremental learning on an embedded edge device with limited resources. The proposed framework is able to achieve two essential tasks, inference and learning, without requiring access to a powerful cloud server. We discuss the design choices made to ensure satisfactory learning performance and efficient resource usage. Experimental results demonstrate the ability of the system to incrementally adapt to unforeseen conditions and to effectively run on a resource-constrained device.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"17 1 1","pages":"61-70"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83213381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00008
B. Ghosh, Clara Hobbs, Shengjie Xu, Parasara Sridhar Duggirala, James H. Anderson, P. Thiagarajan, S. Chakraborty
Software in autonomous systems, owing to performance requirements, is deployed on heterogeneous hardware comprising task specific accelerators, graphical processing units, and multicore processors. But performing timing analysis for safety critical control software tasks with such heterogeneous hardware is becoming increasingly challenging. Consequently, a number of recent papers have addressed the problem of stability analysis of feedback control loops in the presence of timing uncertainties (cf., deadline misses). In this paper, we address a different class of safety properties, viz., whether the system trajectory deviates too much from the nominal trajectory, with the latter computed for the ideal timing behavior. Verifying such quantitative safety properties involves performing a reachability analysis that is computationally intractable, or is too conservative. To alleviate these problems we propose to provide statistical guarantees over behavior of control systems with timing uncertainties. More specifically, we present a Bayesian hypothesis testing method based on Jeffreys’s Bayes factor test that estimates deviations from a nominal or ideal behavior. We show that our analysis can provide, with high confidence, tighter estimates of the deviation from nominal behavior than using known reachability based methods. We also illustrate the scalability of our techniques by obtaining bounds in cases where reachability analysis fails to converge, thereby establishing the former’s practicality.
{"title":"Statistical Hypothesis Testing of Controller Implementations Under Timing Uncertainties","authors":"B. Ghosh, Clara Hobbs, Shengjie Xu, Parasara Sridhar Duggirala, James H. Anderson, P. Thiagarajan, S. Chakraborty","doi":"10.1109/RTCSA55878.2022.00008","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00008","url":null,"abstract":"Software in autonomous systems, owing to performance requirements, is deployed on heterogeneous hardware comprising task specific accelerators, graphical processing units, and multicore processors. But performing timing analysis for safety critical control software tasks with such heterogeneous hardware is becoming increasingly challenging. Consequently, a number of recent papers have addressed the problem of stability analysis of feedback control loops in the presence of timing uncertainties (cf., deadline misses). In this paper, we address a different class of safety properties, viz., whether the system trajectory deviates too much from the nominal trajectory, with the latter computed for the ideal timing behavior. Verifying such quantitative safety properties involves performing a reachability analysis that is computationally intractable, or is too conservative. To alleviate these problems we propose to provide statistical guarantees over behavior of control systems with timing uncertainties. More specifically, we present a Bayesian hypothesis testing method based on Jeffreys’s Bayes factor test that estimates deviations from a nominal or ideal behavior. We show that our analysis can provide, with high confidence, tighter estimates of the deviation from nominal behavior than using known reachability based methods. We also illustrate the scalability of our techniques by obtaining bounds in cases where reachability analysis fails to converge, thereby establishing the former’s practicality.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"7 1","pages":"11-20"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89704618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00024
C. Shih, Hsiang-Jui Lin, Yuyuan Yuan, Yi-Hung Kuo, Wen-Yew Liang
The enhanced computing platforms, which are on edge networks and used for embedding computing services, enable the processing of sensing data on edge and sharing the data with the peers of interest. Smart factories and autonomous vehicles are two typical examples. However, existing real-time communication protocols have limits on cross-network domains and complex data structures. To resolve the problems above, this work investigates a new distributed data exchange framework, Zenoh. As a unified and transparent middle-ware for devices over heterogeneous networks, Zenoh enables peers in different network domains to exchange messages in real-time by pub/sub data exchange pattern. Furthermore, it provides high flexibility and scalability by configurable end-to-end and hop-to-hop reliability and congestion control QoS profiles. This work proposes a bounded-time decision algorithm by Reliable Broadcast and CRDT based on Zenoh. This work also benchmarks the protocol’s capability over cross-domain networks and investigate the overhead of our algorithms implemented on Zenoh. The throughput and latency performance shows the potential for practical communication between robots in factories or autonomous vehicles on roads.
{"title":"Scalable and Bounded-time Decisions on Edge Device Network using Eclipse Zenoh","authors":"C. Shih, Hsiang-Jui Lin, Yuyuan Yuan, Yi-Hung Kuo, Wen-Yew Liang","doi":"10.1109/RTCSA55878.2022.00024","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00024","url":null,"abstract":"The enhanced computing platforms, which are on edge networks and used for embedding computing services, enable the processing of sensing data on edge and sharing the data with the peers of interest. Smart factories and autonomous vehicles are two typical examples. However, existing real-time communication protocols have limits on cross-network domains and complex data structures. To resolve the problems above, this work investigates a new distributed data exchange framework, Zenoh. As a unified and transparent middle-ware for devices over heterogeneous networks, Zenoh enables peers in different network domains to exchange messages in real-time by pub/sub data exchange pattern. Furthermore, it provides high flexibility and scalability by configurable end-to-end and hop-to-hop reliability and congestion control QoS profiles. This work proposes a bounded-time decision algorithm by Reliable Broadcast and CRDT based on Zenoh. This work also benchmarks the protocol’s capability over cross-domain networks and investigate the overhead of our algorithms implemented on Zenoh. The throughput and latency performance shows the potential for practical communication between robots in factories or autonomous vehicles on roads.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"20 1","pages":"170-179"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81709097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00007
M. Sudvarg, Chris Gill
Component-based design can encapsulate and isolate state and the operations on it, but timing semantics crosscut these boundaries when a real-time task’s control flow spans multiple components. Under priority-based scheduling, inter-component control flow should be coupled with priority information, so that task execution can be prioritized appropriately end-to-end. However, the CAmkES component architecture for the seL4 microkernel does not adequately support priority propagation across intercomponent requests: component interfaces are bound to threads that execute at fixed priorities provided at compile-time in the component specification. In this paper, we present a new library for CAmkES with a thread model that supports (1) multiple concurrent requests to the same component endpoint; (2) propagation and enforcement of priority metadata, such that those requests are appropriately prioritized; and (3) implementations of Non-Preemptive Critical Sections, the Immediate Priority Ceiling Protocol and the Priority Inheritance Protocol for components encapsulating critical sections of exclusive access to a shared resource. We measure overheads and blocking times for these new features and use existing theory to perform schedulability analysis. Evaluations on both Intel x86 and ARM platforms show that our new library allows CAmkES to provide suitable end-to-end timing for real-time systems.
{"title":"A Concurrency Framework for Priority-Aware Intercomponent Requests in CAmkES on seL4","authors":"M. Sudvarg, Chris Gill","doi":"10.1109/RTCSA55878.2022.00007","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00007","url":null,"abstract":"Component-based design can encapsulate and isolate state and the operations on it, but timing semantics crosscut these boundaries when a real-time task’s control flow spans multiple components. Under priority-based scheduling, inter-component control flow should be coupled with priority information, so that task execution can be prioritized appropriately end-to-end. However, the CAmkES component architecture for the seL4 microkernel does not adequately support priority propagation across intercomponent requests: component interfaces are bound to threads that execute at fixed priorities provided at compile-time in the component specification. In this paper, we present a new library for CAmkES with a thread model that supports (1) multiple concurrent requests to the same component endpoint; (2) propagation and enforcement of priority metadata, such that those requests are appropriately prioritized; and (3) implementations of Non-Preemptive Critical Sections, the Immediate Priority Ceiling Protocol and the Priority Inheritance Protocol for components encapsulating critical sections of exclusive access to a shared resource. We measure overheads and blocking times for these new features and use existing theory to perform schedulability analysis. Evaluations on both Intel x86 and ARM platforms show that our new library allows CAmkES to provide suitable end-to-end timing for real-time systems.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"116 1","pages":"1-10"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81395796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00011
M. Dobes, P. Zaykov, Larry Miller, Pavel Badin, S. Varadarajan
In the safety-critical domain, such as avionics, there is a strong demand for increased guaranteed performance and lower development costs. This demand is satisfied by utilizing commercial off-the-shelf (COTS) Multiprocessor System-on-Chips (MPSoC). MPSoCs contain multi-core processors that pose a significant challenge for deployment in safety-critical systems, since the Worst-Case Execution Time (WCET) of a process may be influenced by other processes due to cross-core interference.In this paper, we introduce a novel non-intrusive IP Core for Cache and Memory Thrashing (referred to as IP-CMT) that helps us estimate the cross-core interference. The IP-CMT core does not require any software changes to be made to the system under test, resulting in lower development costs. Furthermore, our evaluation with a real-world aerospace-grade Flight Management System indicates that the proposed IP-CMT core is capable of introducing the same degree of cross-core interference as present-day SW methods while not being overly conservative and having minimal overhead. Thus, system performance is spared.
{"title":"IP Core for Cache and Memory Thrashing","authors":"M. Dobes, P. Zaykov, Larry Miller, Pavel Badin, S. Varadarajan","doi":"10.1109/RTCSA55878.2022.00011","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00011","url":null,"abstract":"In the safety-critical domain, such as avionics, there is a strong demand for increased guaranteed performance and lower development costs. This demand is satisfied by utilizing commercial off-the-shelf (COTS) Multiprocessor System-on-Chips (MPSoC). MPSoCs contain multi-core processors that pose a significant challenge for deployment in safety-critical systems, since the Worst-Case Execution Time (WCET) of a process may be influenced by other processes due to cross-core interference.In this paper, we introduce a novel non-intrusive IP Core for Cache and Memory Thrashing (referred to as IP-CMT) that helps us estimate the cross-core interference. The IP-CMT core does not require any software changes to be made to the system under test, resulting in lower development costs. Furthermore, our evaluation with a real-world aerospace-grade Flight Management System indicates that the proposed IP-CMT core is capable of introducing the same degree of cross-core interference as present-day SW methods while not being overly conservative and having minimal overhead. Thus, system performance is spared.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"2 1","pages":"41-50"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74944099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00012
Jatin Arora, Syed Aftab Rashid, Cláudio Maia, E. Tovar
The sharing of main memory among concurrently executing tasks on a multicore platform results in increasing the execution times of those tasks in a non-deterministic manner. The use of phased execution models that divide the execution of tasks into distinct execution and memory phase(s), e.g., the PRedictable Execution Model (PREM) and the 3-Phase task model, along with Memory Centric Scheduling (MCS) present a promising solution to reduce main memory interference among tasks.Existing works in the state-of-the-art that focus on MCS have considered (i) a TDMA-based memory scheduler, i.e., tasks’ memory requests are served under a static TDMA schedule, and (ii) Processor-Priority (PP) based memory scheduler, i.e., tasks’ memory requests are served depending on the priority of the processor/core on which the task is executing. This paper extends MCS by considering a Task-Priority (TP) based memory scheduler, i.e., tasks’ memory requests are served under a global priority order depending on the priority of the task that issues the requests. We present an analysis to bound the total memory interference that can be suffered by the tasks under the TPbased MCS. In contrast to the recent works on MCS that considers non-preemptive tasks, our analysis considers limited preemptive scheduling. Additionally, we investigate the impact of different preemption points on the memory interference of tasks. Experimental results show that our proposed TP-based MCS can significantly reduce the memory interference that can be suffered by the tasks in comparison to the PP-based MCS.
{"title":"Analyzing Fixed Task Priority Based Memory Centric Scheduler for the 3-Phase Task Model","authors":"Jatin Arora, Syed Aftab Rashid, Cláudio Maia, E. Tovar","doi":"10.1109/RTCSA55878.2022.00012","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00012","url":null,"abstract":"The sharing of main memory among concurrently executing tasks on a multicore platform results in increasing the execution times of those tasks in a non-deterministic manner. The use of phased execution models that divide the execution of tasks into distinct execution and memory phase(s), e.g., the PRedictable Execution Model (PREM) and the 3-Phase task model, along with Memory Centric Scheduling (MCS) present a promising solution to reduce main memory interference among tasks.Existing works in the state-of-the-art that focus on MCS have considered (i) a TDMA-based memory scheduler, i.e., tasks’ memory requests are served under a static TDMA schedule, and (ii) Processor-Priority (PP) based memory scheduler, i.e., tasks’ memory requests are served depending on the priority of the processor/core on which the task is executing. This paper extends MCS by considering a Task-Priority (TP) based memory scheduler, i.e., tasks’ memory requests are served under a global priority order depending on the priority of the task that issues the requests. We present an analysis to bound the total memory interference that can be suffered by the tasks under the TPbased MCS. In contrast to the recent works on MCS that considers non-preemptive tasks, our analysis considers limited preemptive scheduling. Additionally, we investigate the impact of different preemption points on the memory interference of tasks. Experimental results show that our proposed TP-based MCS can significantly reduce the memory interference that can be suffered by the tasks in comparison to the PP-based MCS.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"25 1","pages":"51-60"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73839941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.1109/RTCSA55878.2022.00022
G. V. D. Brüggen, Jian-Jia Chen, Robert I. Davis
While academia favours general research that is applicable to a large class of systems, this paper highlights the necessity of research into specific scenarios and aims to increase its acceptance in the real-time systems community. We argue that such research is not only motivated by greater applicability to industry, but that specialization can also provide valuable information from a purely academic perspective. In addition, the trade-offs between generalization and specialization are examined, considering not only theoretical performance, but also the impact on essential non-functional properties that are important for industry, namely composability, robustness, extensibility, and parametric simplicity.
{"title":"On the Trade-offs between Generalization and Specialization in Real-Time Systems","authors":"G. V. D. Brüggen, Jian-Jia Chen, Robert I. Davis","doi":"10.1109/RTCSA55878.2022.00022","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00022","url":null,"abstract":"While academia favours general research that is applicable to a large class of systems, this paper highlights the necessity of research into specific scenarios and aims to increase its acceptance in the real-time systems community. We argue that such research is not only motivated by greater applicability to industry, but that specialization can also provide valuable information from a purely academic perspective. In addition, the trade-offs between generalization and specialization are examined, considering not only theoretical performance, but also the impact on essential non-functional properties that are important for industry, namely composability, robustness, extensibility, and parametric simplicity.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"80 1","pages":"148-159"},"PeriodicalIF":0.7,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74242785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：