Analogue diagnosis of CMOS floating gate defect (FGD) using Genetic Algorithms (GAs)

Abstract

As manufacturers go into volume production with 90 nm designs and below, the floating gate defect (FGD) diagnosis has become a challenge in the initial yield ramp. Since floating gate can result in state-holding, intermittent and pattern-dependent fault effects, these models are generally more complex. Consequently, logical testing is proven can not guarantee the detection of the defect. In this paper, analogue diagnosis to the defect based on defective current is proposed. The magnitude of abnormal increased of power supply current is mainly subjected to the specific location in the Circuit Under Test (CUT), magnitude of input voltage and its sequence. Current open defect diagnosis methods are either keep repeating the circuit simulation based on try and error technique which is tedious or consider part of the factors only for the defect. Thus, the diagnosis results from current procedures may not be as accurate as possible and fully covered. In the proposed method, the significant difference of defective current and the magnitude of voltage supply in sequence are considered using optimization of genetic algorithms (GAs). Results show that the proposed method can achieve a very high diagnosis accuracy and simulation time.