DCT Compression of Test Vector in SoC

Abstract

This paper reports results on studies of the problem and demonstrates the feasibility of the suggested methodology with simulation runs on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits. When the storage nears it limit, they then try to reduce those files size to minimum by using data compression software. In this project i proposed a new algorithm for data compression, called DISCRETE COSINE transform. This algorithm will manipulates each bit of data inside file to minimize the size without losing any data after decoding to lossless compression. This basic algorithm is intended to be combining with other data compression algorithms to optimize the compression ratio