The design of a high gain on-chip antenna for SoC application

Yexi Song, Yunqiu Wu, Jie Yang, K. Kang
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引用次数: 15

Abstract

A V-band high gain and high efficiency on-chip antenna in a CMOS 0.18-μm process is presented in this work. High resistivity silicon substrate, dielectric resonator and a layer of off-chip ground are used in this design to enhance the antenna gain and reduce the antenna size. The proposed antenna achieves a maximum gain of 8 dBi with a -10 dB bandwidth of 4 GHz. The peak antenna efficiency is 96.7% and the half-power-beamwidth is 72° and 92° in the E-and H-plane respectively. Moreover, the chip size of the presented antenna is 700 μm × 1250 μm.
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一种适用于SoC的高增益片上天线的设计
本文提出了一种基于CMOS 0.18 μm工艺的v波段高增益高效率片上天线。本设计采用高电阻硅衬底、介电谐振器和片外接地层,提高了天线增益,减小了天线尺寸。该天线的最大增益为8dbi,带宽为4ghz,为- 10db。天线的峰值效率为96.7%,半功率波束宽度在e面和h面分别为72°和92°。该天线的芯片尺寸为700 μm × 1250 μm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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