Design of a 0.005mm2 8.5ENoB 14.9 fJ/conv-step SAR ADC for Biomedical Application

Abstract

This paper presents a differential 62. 5kS/s, 300nW,8bit successive approximation register (SAR) analog-to-digital converters (ADC) in 40nm CMOS technology occupying a silicon area of $0.005\mathrm{m}\mathrm{m}^{2}$. An algorithm that calculates the impact of capacitor mismatch errors and parasitic effects on performance for multi-structure comparison and area optimization has been proposed. The measured FOM of the proposed ADC is 14.9fJ/c-s at 62. 5kS/s with Effective number of bits (ENoB) of 8. 3bits, spurious free dynamic range (SFDR) of 63.34 dB and total harmonic distortion (THD) of 60.9 dB are achieved.