Based on a new type of coaxial ring-tapered TSV structure, an equivalent circuit model of this structure is constructed in this paper to analyze the transmission characteristics. S11 and S21 are obtained with the geometric model and equivalent circuit model simulated by HFSS and ADS respectively. The experimental results show that the two models have a good fitting effect: in the range of 0-40 GHz, the maximum error of S11 is within 8 %; and the maximum error of S21 is within 5 %, which verifies the correctness of the equivalent circuit model. The specific effects of each parasitic parameter on S11 is found that the silicon substrate capacitance has a great impact on high frequency, and Sll can be increased by 0.15 dB with only 1 fF silicon substrate capacitance, and the remaining parasitic parameters have a small impact on S11.
{"title":"Establishment and Analysis of a New Type of TSV Equivalent Circuit Model","authors":"Lei Pan, Zewei Li, Binbin Xu, Luzhou Liu, Zhikuang Cai, Jian Xiao","doi":"10.1109/ICICM54364.2021.9660289","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660289","url":null,"abstract":"Based on a new type of coaxial ring-tapered TSV structure, an equivalent circuit model of this structure is constructed in this paper to analyze the transmission characteristics. S11 and S21 are obtained with the geometric model and equivalent circuit model simulated by HFSS and ADS respectively. The experimental results show that the two models have a good fitting effect: in the range of 0-40 GHz, the maximum error of S11 is within 8 %; and the maximum error of S21 is within 5 %, which verifies the correctness of the equivalent circuit model. The specific effects of each parasitic parameter on S11 is found that the silicon substrate capacitance has a great impact on high frequency, and Sll can be increased by 0.15 dB with only 1 fF silicon substrate capacitance, and the remaining parasitic parameters have a small impact on S11.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85214747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660365
Yang Li, Xiqin Tang, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang
The traditional Booth decoding applied in Radix-4 Booth multiplier algorithm, introduces a lot of complement operations during processing negative partial products, which increases the design complexity and deteriorates the system performance. To handle this issue, combinations of the classification partial products are analyzed to eliminate the complement conversion in certain situations. Based on this algorithm, an improved 16X16 Radix-4 Booth multiplier with a novel two-stage decoding process is proposed. The design is implemented with Synopsys Design Compiler under SMIC CMOS 55nm technology. The synthesis results show that this work has improvement on reducing the power consumption, boosting the working speed, and narrowing the circuit size.
{"title":"Performance Improvement of Radix-4 Booth Multiplier on Negative Partial Products","authors":"Yang Li, Xiqin Tang, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang","doi":"10.1109/ICICM54364.2021.9660365","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660365","url":null,"abstract":"The traditional Booth decoding applied in Radix-4 Booth multiplier algorithm, introduces a lot of complement operations during processing negative partial products, which increases the design complexity and deteriorates the system performance. To handle this issue, combinations of the classification partial products are analyzed to eliminate the complement conversion in certain situations. Based on this algorithm, an improved 16X16 Radix-4 Booth multiplier with a novel two-stage decoding process is proposed. The design is implemented with Synopsys Design Compiler under SMIC CMOS 55nm technology. The synthesis results show that this work has improvement on reducing the power consumption, boosting the working speed, and narrowing the circuit size.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81119143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660302
W. Lai, Y. Mao
This article introduces integrated transmitter for 802.11bgn applications. The proposed integrated transmitter consists of power amplifier (PA) of two-stage monolithic microwave integrated circuit (MMIC) with broadband pre-distorter, band-pass Gm-C filter, distributed single-pole double-throw (SPDT) radio frequency (RF) switching and chip antenna. The PA design presents conversion gain of 20dB, the output 1-dB compression point (OP 1dB) of 20dBm and power added efficiency (PAE) more than 20%, respectively. The presented PA exhibits error vector magnitude (EVM) of 2.9% and adjacent channel power ratio (ACPR) of -25.6dBc. The implemented integrated transmitter using 0. 18um CMOS technology has experimental outdoor/ indoor throughput base on channels, distance and concurrently complies with the 802.11bgn requirement.
{"title":"Power Amplifier of Two-stage MMIC with Filter and Antenna Design for Transmitter Applications","authors":"W. Lai, Y. Mao","doi":"10.1109/ICICM54364.2021.9660302","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660302","url":null,"abstract":"This article introduces integrated transmitter for 802.11bgn applications. The proposed integrated transmitter consists of power amplifier (PA) of two-stage monolithic microwave integrated circuit (MMIC) with broadband pre-distorter, band-pass Gm-C filter, distributed single-pole double-throw (SPDT) radio frequency (RF) switching and chip antenna. The PA design presents conversion gain of 20dB, the output 1-dB compression point (OP 1dB) of 20dBm and power added efficiency (PAE) more than 20%, respectively. The presented PA exhibits error vector magnitude (EVM) of 2.9% and adjacent channel power ratio (ACPR) of -25.6dBc. The implemented integrated transmitter using 0. 18um CMOS technology has experimental outdoor/ indoor throughput base on channels, distance and concurrently complies with the 802.11bgn requirement.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72879376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660335
Shisong Wan, Lu Tang, Xuan Shen
This paper designs an I2C (Inter-Integrated Circuit) interface module. The I2C interface module is used in all digital phase-locked loop (ADPLL). The front-end simulation frequency of the I2C interface module is 100MHz, and adopt the design of host input and output from the slave. The I2C interface module is based on 40nm COMS process and has a total of 55 output pins.
{"title":"The Core Chip Design of Inter-Integrated Circuit in 40nm CMOS","authors":"Shisong Wan, Lu Tang, Xuan Shen","doi":"10.1109/ICICM54364.2021.9660335","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660335","url":null,"abstract":"This paper designs an I2C (Inter-Integrated Circuit) interface module. The I2C interface module is used in all digital phase-locked loop (ADPLL). The front-end simulation frequency of the I2C interface module is 100MHz, and adopt the design of host input and output from the slave. The I2C interface module is based on 40nm COMS process and has a total of 55 output pins.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77076501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660366
Wenming Zheng, Zhiqun Li, Zhennan Li
This paper presents a fully integrated wideband current-mode digital power amplifier (DPA) for digital polar transmitter in a 22nm RF CMOS process. Current-mode class-D configuration and differential cascode structure are used to obtain high efficiency, noise reduction and high output power with limited supply voltage. A three-coil transformer-based output passive network provides power combining and optimum load impedance transformations simultaneously at two operating frequencies. As a proof-of-concept, a 2.4–5.25 GHz wideband DPA is implemented with supply voltage of 1V for driver circuit and 2.5V for power cells. The simulated peak DPA output power is 30.0dBm/27.5dBm at 2.4GHz/5.25GHz. The simulated peak drain efficiency is 49.8% at 2.4GHz.
{"title":"Design of CMOS Digital Power Amplifier Applied in Digital Polarized Transmitter","authors":"Wenming Zheng, Zhiqun Li, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660366","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660366","url":null,"abstract":"This paper presents a fully integrated wideband current-mode digital power amplifier (DPA) for digital polar transmitter in a 22nm RF CMOS process. Current-mode class-D configuration and differential cascode structure are used to obtain high efficiency, noise reduction and high output power with limited supply voltage. A three-coil transformer-based output passive network provides power combining and optimum load impedance transformations simultaneously at two operating frequencies. As a proof-of-concept, a 2.4–5.25 GHz wideband DPA is implemented with supply voltage of 1V for driver circuit and 2.5V for power cells. The simulated peak DPA output power is 30.0dBm/27.5dBm at 2.4GHz/5.25GHz. The simulated peak drain efficiency is 49.8% at 2.4GHz.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82579046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Based on 0.18μm 80V BCD process, a reference voltage generator for GaN HEMT gate driver without high voltage low dropout regulator is designed, which is mainly composed of high-voltage bandgap reference and operational transconductance amplifier. It can achieve a low temperature coefficient with a wide supply voltage range from 5V to 80V in the temperature range from $-25^{circ}mathrm{C}$ to $100^{circ}mathrm{C}$ by curvature compensation technology. The simulated and measured results show that the function of the proposed reference voltage generator is correct, which can well meet the application requirements of 80V GaN HEMT gate driver.
基于0.18μm 80V BCD工艺，设计了一种无高压低降稳压器的GaN HEMT栅极驱动器参考电压发生器，主要由高压带隙参考电压和运算跨导放大器组成。通过曲率补偿技术，在$-25^{circ}}$到$100^{circ}}mathrm{C}$的温度范围内，可实现5V至80V的低温度系数和宽电源电压范围。仿真和实测结果表明，所提出的基准电压发生器功能正确，能够很好地满足80V GaN HEMT栅极驱动器的应用要求。
{"title":"Reference Voltage Generator for 80V GaN HEMT Gate Driver","authors":"Ningye He, De-Zhong Zhou, Li Wang, Yuan Xu, Xiaoxiong He, Zhenhai Chen","doi":"10.1109/ICICM54364.2021.9660339","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660339","url":null,"abstract":"Based on 0.18μm 80V BCD process, a reference voltage generator for GaN HEMT gate driver without high voltage low dropout regulator is designed, which is mainly composed of high-voltage bandgap reference and operational transconductance amplifier. It can achieve a low temperature coefficient with a wide supply voltage range from 5V to 80V in the temperature range from $-25^{circ}mathrm{C}$ to $100^{circ}mathrm{C}$ by curvature compensation technology. The simulated and measured results show that the function of the proposed reference voltage generator is correct, which can well meet the application requirements of 80V GaN HEMT gate driver.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78815597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660356
Zhiqiang Wang, Zhiqun Li, Jiajun Li, Xiaowei Wang, Zhennan Li
This paper presents a $2.4sim 5.25{mathrm {GHz}}$ single to differential low-noise amplifier (balun-LNA) using 22nm CMOS technology. Current-reuse technique is introduced to make a compromise between gain and linearity. A balanced buffer is used to reduce the gain difference and phase difference of the differential outputs. The contradiction between linearity and NF can also be resolved through variable gain control. The post-simulation results show that it achieves a voltage gain of 30. 0dB, an NF of 1. 49dB, the phase mismatch of 0.3°, and the gain mismatch of 0.1 dB in the high-gain mode. The IIP3 is 9. 0dBm, and IP1dB is 3.0 dBm in the low-gain mode. At 1V supply voltage, the power consumption is 1S.43mW, and the layout is 0.63mm2.
{"title":"A 2.4-5.25GHz Balun-LNA in 22nm CMOS Technology","authors":"Zhiqiang Wang, Zhiqun Li, Jiajun Li, Xiaowei Wang, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660356","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660356","url":null,"abstract":"This paper presents a $2.4sim 5.25{mathrm {GHz}}$ single to differential low-noise amplifier (balun-LNA) using 22nm CMOS technology. Current-reuse technique is introduced to make a compromise between gain and linearity. A balanced buffer is used to reduce the gain difference and phase difference of the differential outputs. The contradiction between linearity and NF can also be resolved through variable gain control. The post-simulation results show that it achieves a voltage gain of 30. 0dB, an NF of 1. 49dB, the phase mismatch of 0.3°, and the gain mismatch of 0.1 dB in the high-gain mode. The IIP3 is 9. 0dBm, and IP1dB is 3.0 dBm in the low-gain mode. At 1V supply voltage, the power consumption is 1S.43mW, and the layout is 0.63mm2.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88006582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660275
Jun’an Zhang, Yi Xu, Cong Peng
An optocoupler chip is proposed in this paper based on BiCMOS process. NPN transistors are utilized as input transistors for transimpedance amplifier (TIA) and comparator to achieve low noise and low offset. Darlington composite transistor and NMOS achieve a class AB output driver circuit. The simulation results show that the optocoupler can work in the supply voltage range of 15$sim$30V, and the peak output current can reach 2.85A. Meanwhile, with a 10$Omega$ resistor and a 10nF capacitor in series at output, the measured rise time tr of the output signal is 60ns, the fall time tf is 67.3ns, the rise propagation delay time tPLH is 118ns, and the fall propagation delay time tPHL is 113.8ns.
{"title":"An Optocoupler Chip Design Based on BiCMOS Technology","authors":"Jun’an Zhang, Yi Xu, Cong Peng","doi":"10.1109/ICICM54364.2021.9660275","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660275","url":null,"abstract":"An optocoupler chip is proposed in this paper based on BiCMOS process. NPN transistors are utilized as input transistors for transimpedance amplifier (TIA) and comparator to achieve low noise and low offset. Darlington composite transistor and NMOS achieve a class AB output driver circuit. The simulation results show that the optocoupler can work in the supply voltage range of 15$sim$30V, and the peak output current can reach 2.85A. Meanwhile, with a 10$Omega$ resistor and a 10nF capacitor in series at output, the measured rise time tr of the output signal is 60ns, the fall time tf is 67.3ns, the rise propagation delay time tPLH is 118ns, and the fall propagation delay time tPHL is 113.8ns.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88712778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660298
Yisu Guo, Jing Jin, Haoyu Liu, Jiwei Huang
This paper presents a sigma-delta ADC applied to precision temperature sensors, which using the VPTAT generated by the front-end circuit as the input VREF to read the temperature digitally. A T-switch design with complementary structure is used in the sample-holding circuit, which greatly reduces the number of switches and decreases the distortion caused by charge injection effect and leakage current. This circuit is designed in TSMC 0.18μm CMOS processes. The simulation results show that the static power consumption of the circuit is 6S.S3μW (@27°C) under the supply voltage of 1.SV. In the range of -45°C~85°C, the signal-to-noise and distortion ratio (SNDR) is 89. 2dB, the effective number of bits (ENOB) is 14. 53bits, the oversampling rate (OSR) is 512. The core area of the circuit is 224.4μm× 248.76μm.
{"title":"A Sigma-Delta ADC with Complementary T-Switch","authors":"Yisu Guo, Jing Jin, Haoyu Liu, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660298","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660298","url":null,"abstract":"This paper presents a sigma-delta ADC applied to precision temperature sensors, which using the VPTAT generated by the front-end circuit as the input VREF to read the temperature digitally. A T-switch design with complementary structure is used in the sample-holding circuit, which greatly reduces the number of switches and decreases the distortion caused by charge injection effect and leakage current. This circuit is designed in TSMC 0.18μm CMOS processes. The simulation results show that the static power consumption of the circuit is 6S.S3μW (@27°C) under the supply voltage of 1.SV. In the range of -45°C~85°C, the signal-to-noise and distortion ratio (SNDR) is 89. 2dB, the effective number of bits (ENOB) is 14. 53bits, the oversampling rate (OSR) is 512. The core area of the circuit is 224.4μm× 248.76μm.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75218015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660367
Hongyu Wu, Weishen Chu
The development of fine-linewidth semiconductor manufacturing process imposes additional requirements on the design optimization. This paper proposes and validates a simulation driven design methodology for structural design optimization of chip package integration. Finite Element Analysis method is employed to perform stress simulation for chip packages and then serves as a training dataset generator for machine learning model development. The effects of chip design parameters on the first principal stress are studied. Multiple machine learning algorithms are applied and evaluated as surrogate models for stress prediction. The random forest algorithm is identified to have the best capability to perform stress prediction for chip package integration design.
{"title":"Machine Learning assisted Structural Design Optimization for Flip Chip Packages","authors":"Hongyu Wu, Weishen Chu","doi":"10.1109/ICICM54364.2021.9660367","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660367","url":null,"abstract":"The development of fine-linewidth semiconductor manufacturing process imposes additional requirements on the design optimization. This paper proposes and validates a simulation driven design methodology for structural design optimization of chip package integration. Finite Element Analysis method is employed to perform stress simulation for chip packages and then serves as a training dataset generator for machine learning model development. The effects of chip design parameters on the first principal stress are studied. Multiple machine learning algorithms are applied and evaluated as surrogate models for stress prediction. The random forest algorithm is identified to have the best capability to perform stress prediction for chip package integration design.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84422178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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