Y. Yokoyama, Nybutaka Itoh, Masap Katayama, K. Takashima, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, E. Yamasaki, Masaya Todokoro, Keinosuke Toriyama, H. Miki, M. Yagyu, T. Kobayashi, S. Miyaoka, N. Tamba
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引用次数: 2
Abstract
A 1.8-V embedded 18-Mb DRAM with memory-cell efficiency of 33% that is achieved by a single-side interface architecture has been developed. A 9-ns RAS access time and a 4.6-ns CAS access time that enables a data-translation rate of 40 Gb/s was achieved. To achieve fast access time, it uses a multi-word redundancy scheme and a YS merged sense scheme. Noise restraint capacitors are introduced to reduce the induced noise to as low as 100 mV for simultaneous wide bandwidth operation with VDD of 1.8 V.
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