Pub Date : 2001-03-01DOI: 10.1109/CICC.2000.852663
A. Bosch, M. Borremans, M. Steyaert, W. Sansen
In this paper, a 10 bit 1 GS/s current-steering CMOS D/A converter is presented. The measured INL is better than +/-0.2 LSB. The 1 GS/s conversion rate has been obtained by a fully custom designed thermometer decoder. The dynamic limitations have been solved, resulting in more than 61 dB measured SFDR in the interval from DC to Nyquist at all conversion rates up to 1 GS/s. At this conversion rate, the power consumption equals 110 mW. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.
{"title":"A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter","authors":"A. Bosch, M. Borremans, M. Steyaert, W. Sansen","doi":"10.1109/CICC.2000.852663","DOIUrl":"https://doi.org/10.1109/CICC.2000.852663","url":null,"abstract":"In this paper, a 10 bit 1 GS/s current-steering CMOS D/A converter is presented. The measured INL is better than +/-0.2 LSB. The 1 GS/s conversion rate has been obtained by a fully custom designed thermometer decoder. The dynamic limitations have been solved, resulting in more than 61 dB measured SFDR in the interval from DC to Nyquist at all conversion rates up to 1 GS/s. At this conversion rate, the power consumption equals 110 mW. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"52 1","pages":"265-268"},"PeriodicalIF":0.0,"publicationDate":"2001-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88075338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852659
K. Uyttenhove, A. Marques, M. Steyaert
In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.
{"title":"A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction","authors":"K. Uyttenhove, A. Marques, M. Steyaert","doi":"10.1109/CICC.2000.852659","DOIUrl":"https://doi.org/10.1109/CICC.2000.852659","url":null,"abstract":"In this paper, a 6-bit CMOS analog-to-digital converter (A/D) with a maximum acquisition speed of 1 GHz is presented. The problem of meta-stability has got special attention in this design, since this problem degrades the Spurious-Free Dynamic Range (SFDR) at high sampling frequencies. Measured SNDR (signal to noise plus distortion) is over 30 dB at 500 MHz clock and f/sub IN/=141 kHz. The measured SFDR for input frequencies up to 250 MHz is over 30 dB. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology with double poly and occupies an active area of 0.8 mm/sup 2/.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"26 1","pages":"249-252"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79702117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852703
D. Ham, A. Hajimiri
A complete analysis of noise in CMOS switching mixers using stochastic differential equations (SDE) is presented. The noise figure is calculated using this analysis which takes both cyclostationary noise sources and capacitive high frequency effects into account. The analysis leads to important design implications for mixer design and shows that some commonly-used approximations for mixer noise calculations can be misleading in certain cases even at low frequencies. It is demonstrated that there is an optimum value for the load capacitor leading to minimum noise figure and maximum conversion gain for the mixer.
{"title":"Complete noise analysis for CMOS switching mixers via stochastic differential equations","authors":"D. Ham, A. Hajimiri","doi":"10.1109/CICC.2000.852703","DOIUrl":"https://doi.org/10.1109/CICC.2000.852703","url":null,"abstract":"A complete analysis of noise in CMOS switching mixers using stochastic differential equations (SDE) is presented. The noise figure is calculated using this analysis which takes both cyclostationary noise sources and capacitive high frequency effects into account. The analysis leads to important design implications for mixer design and shows that some commonly-used approximations for mixer noise calculations can be misleading in certain cases even at low frequencies. It is demonstrated that there is an optimum value for the load capacitor leading to minimum noise figure and maximum conversion gain for the mixer.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"5 1","pages":"439-442"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77246734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852732
J. Rael, A. Abidi
There is an unprecedented interest among circuit designers today to obtain insight into the mechanisms of phase noise in LC oscillators. For only with this insight is it possible to optimize oscillator circuits using low-quality integrated resonators to comply with the exacting phase noise specifications of modern wireless systems. In this paper we concentrate on an understanding of the popular differential LC oscillator. We introduce simple models to capture the nonlinear processes that convert voltage or current thermal noise in resistors or transistors into phase noise in the oscillator. The analysis does not require hypothetical elements, such as limiters or amplitude control loops, to fully explain phase noise. A simple expression at the end accurately specifies thermally induced phase noise, and lends substance to Leeson's original hypothesis. Next, the upconversion of flicker noise into phase noise is traced to mechanisms first identified in the 1930's, but apparently since forgotten. Unlike thermally induced phase noise, which appears as phase modulation sidebands, flicker noise is shown to upconvert by bias-dependent frequency modulation. The results are validated against SpectreRF simulations and measurements on two differential CMOS oscillators tuned by resonators with very different Q's.
{"title":"Physical processes of phase noise in differential LC oscillators","authors":"J. Rael, A. Abidi","doi":"10.1109/CICC.2000.852732","DOIUrl":"https://doi.org/10.1109/CICC.2000.852732","url":null,"abstract":"There is an unprecedented interest among circuit designers today to obtain insight into the mechanisms of phase noise in LC oscillators. For only with this insight is it possible to optimize oscillator circuits using low-quality integrated resonators to comply with the exacting phase noise specifications of modern wireless systems. In this paper we concentrate on an understanding of the popular differential LC oscillator. We introduce simple models to capture the nonlinear processes that convert voltage or current thermal noise in resistors or transistors into phase noise in the oscillator. The analysis does not require hypothetical elements, such as limiters or amplitude control loops, to fully explain phase noise. A simple expression at the end accurately specifies thermally induced phase noise, and lends substance to Leeson's original hypothesis. Next, the upconversion of flicker noise into phase noise is traced to mechanisms first identified in the 1930's, but apparently since forgotten. Unlike thermally induced phase noise, which appears as phase modulation sidebands, flicker noise is shown to upconvert by bias-dependent frequency modulation. The results are validated against SpectreRF simulations and measurements on two differential CMOS oscillators tuned by resonators with very different Q's.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"193 1","pages":"569-572"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75854042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852647
P. Su, S. Fung, S. Tang, F. Assaderaghi, C. Hu
BSIMPD, a physics-based SPICE model, is developed for bridging deep-submicron CMOS designs using partially-depleted SOI technologies. Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for a sound base of scalability and robustness, BSIMPD captures SOI-specific dynamic behaviors with its built-in floating-body, self-heating and body-contact models. A parameter-extraction strategy is demonstrated, and the simulation efficiency is studied. The model has been tested extensively within IBM on state-of-the-art high speed SOI technologies. It has been implemented in many circuit simulators.
{"title":"BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs","authors":"P. Su, S. Fung, S. Tang, F. Assaderaghi, C. Hu","doi":"10.1109/CICC.2000.852647","DOIUrl":"https://doi.org/10.1109/CICC.2000.852647","url":null,"abstract":"BSIMPD, a physics-based SPICE model, is developed for bridging deep-submicron CMOS designs using partially-depleted SOI technologies. Formulated on top of the industry-standard bulk-MOSFET model BSIM3v3 for a sound base of scalability and robustness, BSIMPD captures SOI-specific dynamic behaviors with its built-in floating-body, self-heating and body-contact models. A parameter-extraction strategy is demonstrated, and the simulation efficiency is studied. The model has been tested extensively within IBM on state-of-the-art high speed SOI technologies. It has been implemented in many circuit simulators.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"13 1","pages":"197-200"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88876775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852672
P. Siniscalchi, Jeanne K. Pitz, R. Hester, S. M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, D. Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty, Glenn H. Westphal
A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit, 2.208 MSample/s pipeline ADC and a digital low-pass filter. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3 V supply.
{"title":"A CMOS ADSL codec for central office applications","authors":"P. Siniscalchi, Jeanne K. Pitz, R. Hester, S. M. DeSoto, Minsheng Wang, Sucheendran Sridharan, Robert L. Halbach, D. Richardson, W. Bright, M. Sarraj, J. Hellums, C. Betty, Glenn H. Westphal","doi":"10.1109/CICC.2000.852672","DOIUrl":"https://doi.org/10.1109/CICC.2000.852672","url":null,"abstract":"A CMOS central office codec that supports Full Rate and G.Lite ADSL applications is described. The transmit channel consists of application-dependent digital filters, a 14 bit, 8.832 MSample/s current steering DAC, a 1.104 MHz analog filter and a programmable attenuator. The receive channel contains -17.5 to 33.5 dB of programmable gain, a 138 kHz analog low-pass filter, a 14 bit, 2.208 MSample/s pipeline ADC and a digital low-pass filter. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3 V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"228 1","pages":"303-306"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87597949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852696
T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai
This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 /spl mu/m era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher V/sub th/ and thicker T/sub ox/, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed.
{"title":"Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration","authors":"T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai","doi":"10.1109/CICC.2000.852696","DOIUrl":"https://doi.org/10.1109/CICC.2000.852696","url":null,"abstract":"This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for the deep sub-0.1 /spl mu/m era while maintaining the circuit speed. Applying boosted gate voltage on the low leakage switches with higher V/sub th/ and thicker T/sub ox/, extremely low stand-by power for battery type application is achieved, while degradation of circuit performance and an increase of area overhead are sufficiently suppressed. The combination with a negative gate voltage scheme and the application of the boosted voltage scheme to SRAMs are also discussed.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"67 1","pages":"409-412"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76800314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852676
G. Bollati, A. Dati, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli, P. Gadducci, Stefano Marchese, D. Ottini, Valerio Pisati, F. Rezzi, A. Rossi, P. Savo, C. Tonci, R. Castello
A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.
{"title":"A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi","authors":"G. Bollati, A. Dati, G. Betti, I. Bietti, F. Brianti, M. Bruccoleri, M. Coltella, P. Demartini, M. Demicheli, P. Gadducci, Stefano Marchese, D. Ottini, Valerio Pisati, F. Rezzi, A. Rossi, P. Savo, C. Tonci, R. Castello","doi":"10.1109/CICC.2000.852676","DOIUrl":"https://doi.org/10.1109/CICC.2000.852676","url":null,"abstract":"A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"24 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87855070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852698
A. Annema, G. Geelen, P. C. D. Jong
Robust high-voltage tolerant I/O that does not need process options is presented, demonstrated on 5.5 V tolerant open-drain I/O in a 2.5 V 0.25 /spl mu/m CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation, resulting in hundreds of years extrapolated lifetime for 5.5 V pad voltage swing, 2.2 V supply voltage, 10 MHz switching frequency. The shown concepts are also implemented in other types of I/O and can easily be scaled towards newer processes.
在2.5 V 0.25 /spl mu/m CMOS技术中，展示了5.5 V耐受开漏I/O，该I/O不需要工艺选项。电路技术限制了氧化应力和热载流子退化，导致5.5 V焊盘电压摆幅，2.2 V电源电压，10 MHz开关频率的外推寿命为数百年。所示的概念也可以在其他类型的I/O中实现，并且可以很容易地扩展到新的进程。
{"title":"5.5 V tolerant I/O in a 2.5 V 0.25 /spl mu/m CMOS technology","authors":"A. Annema, G. Geelen, P. C. D. Jong","doi":"10.1109/CICC.2000.852698","DOIUrl":"https://doi.org/10.1109/CICC.2000.852698","url":null,"abstract":"Robust high-voltage tolerant I/O that does not need process options is presented, demonstrated on 5.5 V tolerant open-drain I/O in a 2.5 V 0.25 /spl mu/m CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation, resulting in hundreds of years extrapolated lifetime for 5.5 V pad voltage swing, 2.2 V supply voltage, 10 MHz switching frequency. The shown concepts are also implemented in other types of I/O and can easily be scaled towards newer processes.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"2016 1","pages":"417-420"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87826183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-24DOI: 10.1109/CICC.2000.852609
E. Fogleman, Jared Welz, I. Galton
A second-order audio ADC /spl Delta//spl Sigma/ modulator using a low-complexity 33-level second-order mismatch-shaping DAC is presented. The DAC encoder is designed to reduce signal-dependent DAC noise modulation. The prototype was implemented in a 3.3 V 0.5 /spl mu/m single-poly CMOS process, and it achieves 100 dB SINAD and 102 dB DR.
提出了一种采用低复杂度33级二阶失配整形DAC的二阶音频ADC /spl Delta//spl Sigma/调制器。DAC编码器设计用于减少与信号相关的DAC噪声调制。该原型在3.3 V 0.5 /spl mu/m单多CMOS工艺中实现，实现了100 dB SINAD和102 dB DR。
{"title":"An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC","authors":"E. Fogleman, Jared Welz, I. Galton","doi":"10.1109/CICC.2000.852609","DOIUrl":"https://doi.org/10.1109/CICC.2000.852609","url":null,"abstract":"A second-order audio ADC /spl Delta//spl Sigma/ modulator using a low-complexity 33-level second-order mismatch-shaping DAC is presented. The DAC encoder is designed to reduce signal-dependent DAC noise modulation. The prototype was implemented in a 3.3 V 0.5 /spl mu/m single-poly CMOS process, and it achieves 100 dB SINAD and 102 dB DR.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"4 1","pages":"17-20"},"PeriodicalIF":0.0,"publicationDate":"2000-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82051706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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