IP Core for Cache and Memory Thrashing

Abstract

In the safety-critical domain, such as avionics, there is a strong demand for increased guaranteed performance and lower development costs. This demand is satisfied by utilizing commercial off-the-shelf (COTS) Multiprocessor System-on-Chips (MPSoC). MPSoCs contain multi-core processors that pose a significant challenge for deployment in safety-critical systems, since the Worst-Case Execution Time (WCET) of a process may be influenced by other processes due to cross-core interference.In this paper, we introduce a novel non-intrusive IP Core for Cache and Memory Thrashing (referred to as IP-CMT) that helps us estimate the cross-core interference. The IP-CMT core does not require any software changes to be made to the system under test, resulting in lower development costs. Furthermore, our evaluation with a real-world aerospace-grade Flight Management System indicates that the proposed IP-CMT core is capable of introducing the same degree of cross-core interference as present-day SW methods while not being overly conservative and having minimal overhead. Thus, system performance is spared.