Investigation of CMOS Image Sensor dark current reduction by optimizing Interface defect

Abstract

Dark current (DC) was one of the most critical parameters of CMOS image sensors (CIS), and interface defects during semiconductor fabrication process dominate the DC performance. The research investigated Tx Negative-Bias / P-Well and P+ IMP in this paper, and achieved extreme low DC at high temperature of 60 °C. Firstly, Tx negative bias was used to restrict the Poly/Gate OX/Si substrate interface defects. The DC reduced 83.9% while −0.7 V Negative-Bias implemented on Tx. Secondly, P-Well IMP conditions were studied for reducing the Interface defects of shallow trench isolation (STI). The DC could decrease 39.8 mV/s by increasing Boron dosage of P-Well. Thirdly, photodiode surface IMP (P+) was researched. The suppression of DC induced by PD surface interface defects would decrease 20 mV/s with experimental condition.