Pub Date : 2017-05-04DOI: 10.1109/CSTIC.2017.7919883
Yen-Teng Ho, Y. Chu, Lin‐Lung Wei, T. Luong, Chih-Chien Lin, Chun-Hung Cheng, Hung-Ru Hsu, Y. Tu, E. Chang
Wafer sized, high quality continuous films would be a key demand for MoS2 implemented in circuit application. In this study, the growth of few monolayer MoS2 on 4 inches SiO2/Si substrate were demonstrated. The MoS2 thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO3 starting materials by using H2S. The obtained MoS2 thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS2 with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS2 MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.
{"title":"Wafer size MOS2 with few monolayer synthesized by H2S sulfurization","authors":"Yen-Teng Ho, Y. Chu, Lin‐Lung Wei, T. Luong, Chih-Chien Lin, Chun-Hung Cheng, Hung-Ru Hsu, Y. Tu, E. Chang","doi":"10.1109/CSTIC.2017.7919883","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919883","url":null,"abstract":"Wafer sized, high quality continuous films would be a key demand for MoS<inf>2</inf> implemented in circuit application. In this study, the growth of few monolayer Mo<inf>S2</inf> on 4 inches SiO<inf>2</inf>/Si substrate were demonstrated. The MoS<inf>2</inf> thin films were synthesized by sulfurized in a furnace from the ultra-thin MoO<inf>3</inf> starting materials by using H<inf>2</inf>S. The obtained MoS<inf>2</inf> thin film examined by Raman analysis and Photoluminescence (PL), shows the semiconductor nature with direct transition peaks of 1.86 eV and 1.99 eV. The 4∼5 monolayer of MoS<inf>2</inf> with thickness around 2.6 nm is confirmed by cross-sectional view of transmission electron microscopy (TEM). Additionally, the DC characteristics of MoS<inf>2</inf> MOSFETs exhibit at least 2 order in on/off current ratio, demonstrating the feasibility for circuit application.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"65 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83944070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919895
Chih-Chiang Wu, Shyr-Long Jeng
This paper presents the performance of a single-phase full-bridge inverter based on wide-bandgap devices. The control strategy for the full-bridge inverter applies unipolar sinusoidal pulse width modulation. The experimental results demonstrated that a smaller figure of merit is preferred for a more efficient design; specifically, the full-bridge inverter using gallium nitride field effect transistors inside could easily reach 96% efficiency or more within a 100- to 1000-W range.
{"title":"High-performance single-phase full-bridge inverter using gallium nitride field effect transistors","authors":"Chih-Chiang Wu, Shyr-Long Jeng","doi":"10.1109/CSTIC.2017.7919895","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919895","url":null,"abstract":"This paper presents the performance of a single-phase full-bridge inverter based on wide-bandgap devices. The control strategy for the full-bridge inverter applies unipolar sinusoidal pulse width modulation. The experimental results demonstrated that a smaller figure of merit is preferred for a more efficient design; specifically, the full-bridge inverter using gallium nitride field effect transistors inside could easily reach 96% efficiency or more within a 100- to 1000-W range.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"56 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76775534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919821
R. Mavliev
Slurry is one of most critical yield defining components of CMP process and potential source of problems. Timely and proper monitoring of slurry parameters is critical for CMP yield improvement. Slurry is very complex system - the combination of chemistry and nanoparticles with wide range of parameters. Metrology of slurry parameters could be done in 3 levels- supplier manufacturing/delivery site, Slurry Delivery Systems (SDS) in subfab and point-of-use (POU) - CMP tool, with very different time requirements, size and concentration limits on each level.
{"title":"CMP slurry metrology to meet the industry demand","authors":"R. Mavliev","doi":"10.1109/CSTIC.2017.7919821","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919821","url":null,"abstract":"Slurry is one of most critical yield defining components of CMP process and potential source of problems. Timely and proper monitoring of slurry parameters is critical for CMP yield improvement. Slurry is very complex system - the combination of chemistry and nanoparticles with wide range of parameters. Metrology of slurry parameters could be done in 3 levels- supplier manufacturing/delivery site, Slurry Delivery Systems (SDS) in subfab and point-of-use (POU) - CMP tool, with very different time requirements, size and concentration limits on each level.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"35 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77433416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919769
Jian Xu, Long Qin, Qiaoli Chen, Hui Zhi, Yanyun Wang, Zhengkai Yang, Zhibiao Mao
The overlay control is one of the main challenges for advanced lithography in sub-28 nm technology node. There are two kind of overlay metrology in use in semiconductor industry: most conventional image-based overlay (IBO) metrology and advanced diffraction-based overlay(DBO) metrology. In this paper we will compare these two methods through 3 critical production layers, focusing on the accuracy and the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. The results show that both the accuracy and TMU of DBO method are superior to the traditional IBO method, which makes DBO method applicable at the 28nm and below technology node.
{"title":"Diffraction-based and image-based overlay evaluation for advanced technology node","authors":"Jian Xu, Long Qin, Qiaoli Chen, Hui Zhi, Yanyun Wang, Zhengkai Yang, Zhibiao Mao","doi":"10.1109/CSTIC.2017.7919769","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919769","url":null,"abstract":"The overlay control is one of the main challenges for advanced lithography in sub-28 nm technology node. There are two kind of overlay metrology in use in semiconductor industry: most conventional image-based overlay (IBO) metrology and advanced diffraction-based overlay(DBO) metrology. In this paper we will compare these two methods through 3 critical production layers, focusing on the accuracy and the total measurement uncertainty (TMU) for the standard overlay targets of both techniques. The results show that both the accuracy and TMU of DBO method are superior to the traditional IBO method, which makes DBO method applicable at the 28nm and below technology node.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"55 ","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91455294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919844
Cheng Xu, Z. Zhong, W. Choi
Fan-out wafer level packaging technology becomes attractive because of its flexibility for integration of diverse devices in a small form factor. In this study, the effect of high temperature storage test on fan-out wafer level package strength was evaluated. There were three different structure fan-out wafer level packages. The high temperature storage reliability test was used to store the specimens up to 1000 hours. The three-point bending test method was conducted to evaluate the specimen flexure strength. The experiment results showed that FOWLP flexure strength increased with the high temperature storage test time increasing.
{"title":"Effect of high temperature storage on fan-out wafer level package strength","authors":"Cheng Xu, Z. Zhong, W. Choi","doi":"10.1109/CSTIC.2017.7919844","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919844","url":null,"abstract":"Fan-out wafer level packaging technology becomes attractive because of its flexibility for integration of diverse devices in a small form factor. In this study, the effect of high temperature storage test on fan-out wafer level package strength was evaluated. There were three different structure fan-out wafer level packages. The high temperature storage reliability test was used to store the specimens up to 1000 hours. The three-point bending test method was conducted to evaluate the specimen flexure strength. The experiment results showed that FOWLP flexure strength increased with the high temperature storage test time increasing.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89924205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919730
Jong-Ho Lee, Ho-Jung Kang
We extract the trap density (Nt) profile of the nitride storage layer in 3-D NAND flash memory cells. The adjacent cells which are programmed suppress significantly the lateral diffusion during retention measurement so that we can extract accurate Nt profile. The AC-gm method makes the Nt profiling in an EC-ET range of 1∼1.2 eV possible, and provides a Gaussian Nt profile together with the retention model. The threshold voltage shift with trapped electron profiles is firstly modeled as a parameter of channel radius and its model is verified.
{"title":"Investigation of trap profile in nitride charge trap layer in 3-D NAND flash memory cells","authors":"Jong-Ho Lee, Ho-Jung Kang","doi":"10.1109/CSTIC.2017.7919730","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919730","url":null,"abstract":"We extract the trap density (N<inf>t</inf>) profile of the nitride storage layer in 3-D NAND flash memory cells. The adjacent cells which are programmed suppress significantly the lateral diffusion during retention measurement so that we can extract accurate N<inf>t</inf> profile. The AC-g<inf>m</inf> method makes the N<inf>t</inf> profiling in an E<inf>C</inf>-E<inf>T</inf> range of 1∼1.2 eV possible, and provides a Gaussian N<inf>t</inf> profile together with the retention model. The threshold voltage shift with trapped electron profiles is firstly modeled as a parameter of channel radius and its model is verified.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80361030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919743
P. Fay, W. Li, D. Digiovanni, L. Cao, H. Ilatikhameneh, F. Chen, T. Ameen, R. Rahman, Gerhard Klimeck, C. Lund, S. Keller, S. M. Islam, A. Chaney, Y. Cho, D. Jena
Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.
{"title":"III-N heterostructure devices for low-power logic","authors":"P. Fay, W. Li, D. Digiovanni, L. Cao, H. Ilatikhameneh, F. Chen, T. Ameen, R. Rahman, Gerhard Klimeck, C. Lund, S. Keller, S. M. Islam, A. Chaney, Y. Cho, D. Jena","doi":"10.1109/CSTIC.2017.7919743","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919743","url":null,"abstract":"Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87542392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919817
Fan Bai, Zhijie Zhang, Jia Wang, Hongdi Wang
Shallow trench isolation chemical mechanical polishing (STICMP) technology has been widely applied in the fabrication of ultra large scale integrated (ULSI). In STI-CMP, the defect, topography control, thickness uniformity and so on are all so critical, especially, scratch defect is the major problem. Pad, disk, agglomerated slurry particles and foreign particles are the main sources of the tiny scratch. In this article, impact of transfer process on scratch during STI-CMP, such as pre CMP, bulk polish post treatment, and pre selective polish was studied. Variable down force, DIW rinse time, slurry flow rate, slurry buff treatment were verified respectively. It was found that the pre CMP slurry buff can reduce the scratch by 55%, and bulk polish post step with optimized buff condition also can reduce scratch by 30%. Besides, the backside clean also can reduce the scratch significantly.
{"title":"Impact of wafer transfer process on STI CMP scratches","authors":"Fan Bai, Zhijie Zhang, Jia Wang, Hongdi Wang","doi":"10.1109/CSTIC.2017.7919817","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919817","url":null,"abstract":"Shallow trench isolation chemical mechanical polishing (STICMP) technology has been widely applied in the fabrication of ultra large scale integrated (ULSI). In STI-CMP, the defect, topography control, thickness uniformity and so on are all so critical, especially, scratch defect is the major problem. Pad, disk, agglomerated slurry particles and foreign particles are the main sources of the tiny scratch. In this article, impact of transfer process on scratch during STI-CMP, such as pre CMP, bulk polish post treatment, and pre selective polish was studied. Variable down force, DIW rinse time, slurry flow rate, slurry buff treatment were verified respectively. It was found that the pre CMP slurry buff can reduce the scratch by 55%, and bulk polish post step with optimized buff condition also can reduce scratch by 30%. Besides, the backside clean also can reduce the scratch significantly.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89298607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fingerprint sensor (FPS) becomes rapidly popular due to small size and high safety. The molding thickness of capacitive FPS will affect its performance and needs to be accurately measured and controlled. Different from cutting and laser drilling method, one none destructive method with Terahertz electromagnetic wave is introduced. Terahertz wave can penetrate into the molding package materials. The molding thickness can be measured through time delay of two pulse Terahertz waves. The measured thickness is correlated with microscope view and the result is within ±4um gap.
{"title":"Finger print sensor molding thickness none destructive measurement with Terahertz technology","authors":"Longhai Liu, Haitao Jiang, Ying Wang, Qinghua Shou, Jianhua Xie, Yaqi Lu","doi":"10.1109/CSTIC.2017.7919842","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919842","url":null,"abstract":"Fingerprint sensor (FPS) becomes rapidly popular due to small size and high safety. The molding thickness of capacitive FPS will affect its performance and needs to be accurately measured and controlled. Different from cutting and laser drilling method, one none destructive method with Terahertz electromagnetic wave is introduced. Terahertz wave can penetrate into the molding package materials. The molding thickness can be measured through time delay of two pulse Terahertz waves. The measured thickness is correlated with microscope view and the result is within ±4um gap.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"84 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74608052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919754
H. Yu, Yueyu Zhang, Bin-Jie Jiang, Shirui Yu, Zhibiao Mao
The source-mask optimization (SMO) solution has become one of the most important branches of Resolution enhancement techniques (RET) to extend the imaging process window with next generation computation lithography, which improve the imaging capability of lithographic systems in the integrated circuit foundry manufacturing. Based on the SMO software RET Selection provided by Mentor Graphics Corporation, we have researched the SMO process to improve the imaging capability of lithographic systems for 28nm node and beyond: choosing the key patterns, confirming the process window conditions and so on. In this paper, the parameters PV band, MEEF, NILS and DOF have been used to evaluate the free form illumination sources, and the final illumination source have been verified, which generated by ASML scanner.
{"title":"Research of SMO process to improve the imaging capability of lithography system for 28nm node and beyond","authors":"H. Yu, Yueyu Zhang, Bin-Jie Jiang, Shirui Yu, Zhibiao Mao","doi":"10.1109/CSTIC.2017.7919754","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919754","url":null,"abstract":"The source-mask optimization (SMO) solution has become one of the most important branches of Resolution enhancement techniques (RET) to extend the imaging process window with next generation computation lithography, which improve the imaging capability of lithographic systems in the integrated circuit foundry manufacturing. Based on the SMO software RET Selection provided by Mentor Graphics Corporation, we have researched the SMO process to improve the imaging capability of lithographic systems for 28nm node and beyond: choosing the key patterns, confirming the process window conditions and so on. In this paper, the parameters PV band, MEEF, NILS and DOF have been used to evaluate the free form illumination sources, and the final illumination source have been verified, which generated by ASML scanner.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"33 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74625051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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