{"title":"ATM switching based on deflection routing","authors":"A. Pattavina","doi":"10.1109/SCAC.1995.523653","DOIUrl":null,"url":null,"abstract":"ATM switch architectures based on deflection routing are examined and compared with regards to their internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where conflicts for the same internal link are dealt with, stage by stage, by deflecting the packets onto the wrong path. The main engineering parameter of the architecture, that is the number of network stages that provides a given packet loss performance, is studied. In particular it is found that basically all the examined architectures have a complexity on the order of Nlog/sub 2/N in the range of switch sizes of usual interest. Furthermore it has been possible to rank the architectures with comparable complexity based on the loss performance they provide.","PeriodicalId":90699,"journal":{"name":"Proceedings. IEEE Symposium on Computers and Communications","volume":"55 1","pages":"98-104"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Symposium on Computers and Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCAC.1995.523653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
ATM switch architectures based on deflection routing are examined and compared with regards to their internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where conflicts for the same internal link are dealt with, stage by stage, by deflecting the packets onto the wrong path. The main engineering parameter of the architecture, that is the number of network stages that provides a given packet loss performance, is studied. In particular it is found that basically all the examined architectures have a complexity on the order of Nlog/sub 2/N in the range of switch sizes of usual interest. Furthermore it has been possible to rank the architectures with comparable complexity based on the loss performance they provide.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
