A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS

Ilter Özkaya, A. Cevrero, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, L. Kull, M. Kossel, D. Luu, M. Meghelli, Y. Leblebici, T. Toifl
{"title":"A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS","authors":"Ilter Özkaya, A. Cevrero, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, L. Kull, M. Kossel, D. Luu, M. Meghelli, Y. Leblebici, T. Toifl","doi":"10.1109/ISSCC.2018.8310286","DOIUrl":null,"url":null,"abstract":"The increasing bandwidth demand in data-centers requires wireline transceivers supporting >50Gb/s/lane data-rates with low power consumption. Because link utilization in data-centers is <10% for 99% of the links [1] a promising way to reduce power consumption is fine-grained power gating, where the link is powered off during idle time. For rapid on/off functionality to be efficient with short data bursts, the link needs to wake up within a few ns, which is challenging at high speeds. Burst mode operation was previously demonstrated at 25Gb/s with 18.5ns lock-time [2] without power cycling.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"36 1","pages":"266-268"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2018.8310286","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20

Abstract

The increasing bandwidth demand in data-centers requires wireline transceivers supporting >50Gb/s/lane data-rates with low power consumption. Because link utilization in data-centers is <10% for 99% of the links [1] a promising way to reduce power consumption is fine-grained power gating, where the link is powered off during idle time. For rapid on/off functionality to be efficient with short data bursts, the link needs to wake up within a few ns, which is challenging at high speeds. Burst mode operation was previously demonstrated at 25Gb/s with 18.5ns lock-time [2] without power cycling.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
56Gb/s突发模式NRZ光接收机,上电6.8ns, CDR-Lock时间,用于14nm FinFET CMOS自适应光链路
数据中心日益增长的带宽需求要求有线收发器支持>50Gb/s/lane数据速率和低功耗。由于数据中心中99%的链路利用率<10%[1],因此降低功耗的一种很有希望的方法是细粒度电源门控,即在空闲时间关闭链路。为了使快速开/关功能在短数据突发下有效,链路需要在几ns内唤醒,这在高速下是具有挑战性的。突发模式的工作速度为25Gb/s,锁定时间为18.5ns[2],无需电源循环。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
EE1: Student research preview (SRP) A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiography A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm3 pressure-sensing system A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1