Pub Date : 2019-02-01DOI: 10.1109/isscc.2018.8310409
T. Mohsenin
The Student Research Preview (SRP) will highlight selected student research projects in progress. The SRP consists of 25 one-minute presentations followed by a Poster Session, by graduate students from around the world, which have been selected on the basis of a short submission concerning their on-going research. Selection is based on the technical quality and innovation of the work. This year, the SRP will be presented in three theme sections: Communications and Power; Deep Learning and Biomedical Circuits; Memory, Sensors, and Mixed-Signal Circuits. The Student Research Preview will include a brief talk by a distinguished member of the solid-state circuits community, Professor Tom Lee, Stanford University. SRP begins at 7:30 pm on Sunday, Febuary 11th. SRP is open to all ISSCC registrants.
{"title":"EE1: Student research preview (SRP)","authors":"T. Mohsenin","doi":"10.1109/isscc.2018.8310409","DOIUrl":"https://doi.org/10.1109/isscc.2018.8310409","url":null,"abstract":"The Student Research Preview (SRP) will highlight selected student research projects in progress. The SRP consists of 25 one-minute presentations followed by a Poster Session, by graduate students from around the world, which have been selected on the basis of a short submission concerning their on-going research. Selection is based on the technical quality and innovation of the work. This year, the SRP will be presented in three theme sections: Communications and Power; Deep Learning and Biomedical Circuits; Memory, Sensors, and Mixed-Signal Circuits. The Student Research Preview will include a brief talk by a distinguished member of the solid-state circuits community, Professor Tom Lee, Stanford University. SRP begins at 7:30 pm on Sunday, Febuary 11th. SRP is open to all ISSCC registrants.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"70 1","pages":"520-522"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86221701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-12DOI: 10.1109/ISSCC.2018.8310321
H. Maejima, K. Kanda, Susumu Fujimura, Teruo Takagiwa, S. Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, R. Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Y. Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, M. Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, N. Kobayashi, M. Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Y. Ochi, Kenro Kubota, T. Wakui, D. He, Weihan Wang, H. Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Y. Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, T. Futatsuyama, K. Hosono, N. Shibata, Toshiki Hisada, T. Kaneko, H. Nakamura
The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart Vt-tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.
{"title":"A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology","authors":"H. Maejima, K. Kanda, Susumu Fujimura, Teruo Takagiwa, S. Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Naohito Morozumi, R. Fukuda, Yuui Shimizu, Toshifumi Hashimoto, Xu Li, Y. Shimizu, Kenichi Abe, Tadashi Yasufuku, Takatoshi Minamoto, Hiroshi Yoshihara, Takahiro Yamashita, Kazuhiko Satou, Takahiro Sugimoto, Fumihiro Kono, Mitsuhiro Abe, Tomoharu Hashiguchi, M. Kojima, Yasuhiro Suematsu, Takahiro Shimizu, Akihiro Imamoto, N. Kobayashi, M. Miakashi, Kouichirou Yamaguchi, Sanad Bushnaq, Hicham Haibi, Masatsugu Ogawa, Y. Ochi, Kenro Kubota, T. Wakui, D. He, Weihan Wang, H. Minagawa, Tomoko Nishiuchi, Hao Nguyen, Kwang-Ho Kim, Ken Cheah, Y. Koh, Feng Lu, Venky Ramachandra, Srinivas Rajendra, Steve Choi, Keyur Payak, Namas Raghunathan, Spiros Georgakis, Hiroshi Sugawara, Seungpil Lee, T. Futatsuyama, K. Hosono, N. Shibata, Toshiki Hisada, T. Kaneko, H. Nakamura","doi":"10.1109/ISSCC.2018.8310321","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310321","url":null,"abstract":"The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, the multi-level-cell technology, which was initially proposed for 2D Flash, has also been adopted to 3D Flash memories. The first 3b/cell 32-layer Flash was presented in 2015 [2], followed by a 48-layer one in 2016 [3], and a 64-layer one in 2017 [4,5]. This paper describes a 512Gb 3b/cell 3D Flash memory in a 96-word-line-layer BiCS FLASH technology. This work implements three key technologies to improve performance: (1) a string based start bias control scheme achieves a 7% shorter program time; (2) a smart Vt-tracking read improves read retry performance by minimizing the tracking time and supporting a program suspend read function, and; (3) a low-pre-charge sense-amplifier bus scheme reduces both the power consumption and the data-transfer time between the sense amplifier (SA) and the data cache by half. Figure 20.1.1 shows the die micrograph and the summary of the key features of the chip.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"336-338"},"PeriodicalIF":0.0,"publicationDate":"2018-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84009150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-12DOI: 10.1109/ISSCC.2018.8310247
Gwangrok Jung, M. W. Rashid, T. Carpenter, C. Tekes, D. Cowell, S. Freear, F. Degertekin, Maysam Ghovanloo
Intracardiac echocardiography (ICE) provides real-time ultrasound imaging of the heart anatomy from inside, guiding interventions like valve repair, closure of atrial septal defects (ASD) and catheter-based ablation to treat atrial fibrillation. With its better image quality and ease of use, ICE is becoming the preferred imaging modality over transesophageal echography (TEE) for structural heart interventions. The existing commercial ICE catheters, however, offer a limited 2-D or 3-D field of view despite catheters utilizing large number of wires. In these catheters, each element in the ICE array is connected to the backend data-acquisition channel with a separate wire, which is a critical barrier for improving image quality and widening the field of view. In order to use ICE catheters under MRI instead of the ionizing X-ray radiation-based angiography, the number of interconnect wires in the catheter should be minimized to reduce RF-induced heating. Furthermore, reducing the number of wires improves the flexibility and lowers the cost of the single-use ICE catheters.
{"title":"Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiography","authors":"Gwangrok Jung, M. W. Rashid, T. Carpenter, C. Tekes, D. Cowell, S. Freear, F. Degertekin, Maysam Ghovanloo","doi":"10.1109/ISSCC.2018.8310247","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310247","url":null,"abstract":"Intracardiac echocardiography (ICE) provides real-time ultrasound imaging of the heart anatomy from inside, guiding interventions like valve repair, closure of atrial septal defects (ASD) and catheter-based ablation to treat atrial fibrillation. With its better image quality and ease of use, ICE is becoming the preferred imaging modality over transesophageal echography (TEE) for structural heart interventions. The existing commercial ICE catheters, however, offer a limited 2-D or 3-D field of view despite catheters utilizing large number of wires. In these catheters, each element in the ICE array is connected to the backend data-acquisition channel with a separate wire, which is a critical barrier for improving image quality and widening the field of view. In order to use ICE catheters under MRI instead of the ionizing X-ray radiation-based angiography, the number of interconnect wires in the catheter should be minimized to reduce RF-induced heating. Furthermore, reducing the number of wires improves the flexibility and lowers the cost of the single-use ICE catheters.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"5 1","pages":"188-190"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83756799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310229
S. Du, A. Seshia
Along with the development of the Internet of Everything (IoE), miniaturized piezoelectric vibration-energy harvesters have drawn significant recent interest as a means of harvesting ambient kinetic energy to power wireless sensors. As the energy generated by a piezoelectric transducer (PT) cannot be directly used, an interface circuit is needed to rectify the generated power and provide a stable supply. Full-bridge rectifiers (FBR) are widely used due to their simplicity despite their low energy efficiency. Recently, various interface circuits have been reported [1-5] to improve power efficiency, such as the SSHI (Synchronized Switch Harvesting on Inductor) rectifier. However, most of these reported circuits require large inductors to achieve good performance, and these inductors significantly increase the system volume, counter to the requirement for system miniaturization. Although a flipping-capacitor rectifier was proposed in [2] to flip voltages using on-chip capacitors, it was designed for high frequency (>100kHz) ultrasonic energy transfer applications and does not work with PTs with a large internal capacitor CP since the values of the capacitors required are too large for on-chip implementation. Another inductorless circuit, named SSHC (synchronized switch harvesting on capacitors), was recently proposed in [1] (Fig. 8.9.1); however, the required switched-capacitor (SC) values must equal CP to achieve optimal performance and this limits the on-chip implementation for PTs with large CP capacitance.
{"title":"A fully integrated split-electrode synchronized-switch-harvesting-on-capacitors (SE-SSHC) rectifier for piezoelectric energy harvesting with between 358% and 821% power-extraction enhancement","authors":"S. Du, A. Seshia","doi":"10.1109/ISSCC.2018.8310229","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310229","url":null,"abstract":"Along with the development of the Internet of Everything (IoE), miniaturized piezoelectric vibration-energy harvesters have drawn significant recent interest as a means of harvesting ambient kinetic energy to power wireless sensors. As the energy generated by a piezoelectric transducer (PT) cannot be directly used, an interface circuit is needed to rectify the generated power and provide a stable supply. Full-bridge rectifiers (FBR) are widely used due to their simplicity despite their low energy efficiency. Recently, various interface circuits have been reported [1-5] to improve power efficiency, such as the SSHI (Synchronized Switch Harvesting on Inductor) rectifier. However, most of these reported circuits require large inductors to achieve good performance, and these inductors significantly increase the system volume, counter to the requirement for system miniaturization. Although a flipping-capacitor rectifier was proposed in [2] to flip voltages using on-chip capacitors, it was designed for high frequency (>100kHz) ultrasonic energy transfer applications and does not work with PTs with a large internal capacitor CP since the values of the capacitors required are too large for on-chip implementation. Another inductorless circuit, named SSHC (synchronized switch harvesting on capacitors), was recently proposed in [1] (Fig. 8.9.1); however, the required switched-capacitor (SC) values must equal CP to achieve optimal performance and this limits the on-chip implementation for PTs with large CP capacitance.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"32 1","pages":"152-154"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85299481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For deep-neural-network (DNN) processors [1-4], the product-sum (PS) operation predominates the computational workload for both convolution (CNVL) and fully-connect (FCNL) neural-network (NN) layers. This hinders the adoption of DNN processors to on the edge artificial-intelligence (AI) devices, which require low-power, low-cost and fast inference. Binary DNNs [5-6] are used to reduce computation and hardware costs for AI edge devices; however, a memory bottleneck still remains. In Fig. 31.5.1 conventional PE arrays exploit parallelized computation, but suffer from inefficient single-row SRAM access to weights and intermediate data. Computing-in-memory (CIM) improves efficiency by enabling parallel computing, reducing memory accesses, and suppressing intermediate data. Nonetheless, three critical challenges remain (Fig. 31.5.2), particularly for FCNL. We overcome these problems by co-optimizing the circuits and the system. Recently, researches have been focusing on XNOR based binary-DNN structures [6]. Although they achieve a slightly higher accuracy, than other binary structures, they require a significant hardware cost (i.e. 8T-12T SRAM) to implement a CIM system. To further reduce the hardware cost, by using 6T SRAM to implement a CIM system, we employ binary DNN with 0/1-neuron and ±1-weight that was proposed in [7]. We implemented a 65nm 4Kb algorithm-dependent CIM-SRAM unit-macro and in-house binary DNN structure (focusing on FCNL with a simplified PE array), for cost-aware DNN AI edge processors. This resulted in the first binary-based CIM-SRAM macro with the fastest (2.3ns) PS operation, and the highest energy-efficiency (55.8TOPS/W) among reported CIM macros [3-4].
{"title":"A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors","authors":"W. Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang","doi":"10.1109/ISSCC.2018.8310401","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310401","url":null,"abstract":"For deep-neural-network (DNN) processors [1-4], the product-sum (PS) operation predominates the computational workload for both convolution (CNVL) and fully-connect (FCNL) neural-network (NN) layers. This hinders the adoption of DNN processors to on the edge artificial-intelligence (AI) devices, which require low-power, low-cost and fast inference. Binary DNNs [5-6] are used to reduce computation and hardware costs for AI edge devices; however, a memory bottleneck still remains. In Fig. 31.5.1 conventional PE arrays exploit parallelized computation, but suffer from inefficient single-row SRAM access to weights and intermediate data. Computing-in-memory (CIM) improves efficiency by enabling parallel computing, reducing memory accesses, and suppressing intermediate data. Nonetheless, three critical challenges remain (Fig. 31.5.2), particularly for FCNL. We overcome these problems by co-optimizing the circuits and the system. Recently, researches have been focusing on XNOR based binary-DNN structures [6]. Although they achieve a slightly higher accuracy, than other binary structures, they require a significant hardware cost (i.e. 8T-12T SRAM) to implement a CIM system. To further reduce the hardware cost, by using 6T SRAM to implement a CIM system, we employ binary DNN with 0/1-neuron and ±1-weight that was proposed in [7]. We implemented a 65nm 4Kb algorithm-dependent CIM-SRAM unit-macro and in-house binary DNN structure (focusing on FCNL with a simplified PE array), for cost-aware DNN AI edge processors. This resulted in the first binary-based CIM-SRAM macro with the fastest (2.3ns) PS operation, and the highest energy-efficiency (55.8TOPS/W) among reported CIM macros [3-4].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"11 1","pages":"496-498"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88723243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310387
Y. Jia, S. Mirbozorgi, Byunghun Lee, W. Khan, F. Madi, A. Weber, Wen Li, Maysam Ghovanloo
Thanks to its cell-type specificity, high spatiotemporal precision, and reversibility, optogenetic neuromodulation has been widely utilized in brain mapping, visual prostheses, psychological disorders, Parkinson's disease, epilepsy, and cardiac electrophysiology [1]. While a variety of optical neural interfaces have been developed, most have substantial limitations due to their size and tethering, needed to either deliver light or electricity, which may restrict the animal movements and bias the results, particularly in behavioral studies. In contrast, wirelessly powered optogenetic interfaces improve accuracy, reliability, and validity of the outcomes by eliminating tethers. Recently, a few wirelessly powered optogenetics approaches have been reported with impressive reduction in size of the implant [2]. However, their practical application is impeded by requiring high operating frequencies in GHz range, which increases the risk of exposure to unsafe electromagnetic specific absorption rates (SAR), resulting in excessive heat generation. They also lack proper control over optical stimulus characteristics. Towards this end, we propose a practical mm-sized Free-Floating Wirelessly-powered implantable Optical Stimulating (FF-WIOS) SoC to not only eliminate the tethering effects but also reduce the level of invasiveness and SAR in the tissue.
{"title":"A mm-sized free-floating wirelessly powered implantable optical stimulating system-on-a-chip","authors":"Y. Jia, S. Mirbozorgi, Byunghun Lee, W. Khan, F. Madi, A. Weber, Wen Li, Maysam Ghovanloo","doi":"10.1109/ISSCC.2018.8310387","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310387","url":null,"abstract":"Thanks to its cell-type specificity, high spatiotemporal precision, and reversibility, optogenetic neuromodulation has been widely utilized in brain mapping, visual prostheses, psychological disorders, Parkinson's disease, epilepsy, and cardiac electrophysiology [1]. While a variety of optical neural interfaces have been developed, most have substantial limitations due to their size and tethering, needed to either deliver light or electricity, which may restrict the animal movements and bias the results, particularly in behavioral studies. In contrast, wirelessly powered optogenetic interfaces improve accuracy, reliability, and validity of the outcomes by eliminating tethers. Recently, a few wirelessly powered optogenetics approaches have been reported with impressive reduction in size of the implant [2]. However, their practical application is impeded by requiring high operating frequencies in GHz range, which increases the risk of exposure to unsafe electromagnetic specific absorption rates (SAR), resulting in excessive heat generation. They also lack proper control over optical stimulus characteristics. Towards this end, we propose a practical mm-sized Free-Floating Wirelessly-powered implantable Optical Stimulating (FF-WIOS) SoC to not only eliminate the tethering effects but also reduce the level of invasiveness and SAR in the tissue.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"15 1","pages":"468-470"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90227402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310307
Somnath Kundu, Muqing Liu, R. Wong, Shi-Jie Wen, C. Kim
Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (DVFS). Low Dropout Regulators (LDOs) based on digital-intensive circuits have been gaining popularity [1]-[4] due to their compactness, process scalability, high immunity to process-voltage-temperature (PVT) variations and easy programmability for design optimization. Conventional digital LDOs utilizing a comparator and shift-registers [1] suffer from a slow response time during a large/fast change in load current (Iload). Higher sampling frequency (fS) improves the response time, but at the cost of increased power consumption and reduced loop stability. Multi-bit quantizers utilizing ADCs [2-4] can reduce the settling time, however, the presence of a high resolution ADC and the control logic increases the design complexity. Moreover, the ADC resolution limits the maximum fS. In order to overcome the trade-off between speed and power, adaptive sampling techniques were incorporated in [1], [4]. But the overhead of multiple VCOs operating simultaneously and a separate overshoot/droop detection circuitry [1], or an event-driven controller with 7b ADC [4], increase the complexity and power consumption. Furthermore, none of the previous designs incorporated active voltage positioning (AVP), a popular ripple-suppression technique, whereby the LDO output is set slightly above (in low-activity state) or below (in high-activity state) the reference voltage depending on the processor workload conditions [5].
{"title":"A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning","authors":"Somnath Kundu, Muqing Liu, R. Wong, Shi-Jie Wen, C. Kim","doi":"10.1109/ISSCC.2018.8310307","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310307","url":null,"abstract":"Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (DVFS). Low Dropout Regulators (LDOs) based on digital-intensive circuits have been gaining popularity [1]-[4] due to their compactness, process scalability, high immunity to process-voltage-temperature (PVT) variations and easy programmability for design optimization. Conventional digital LDOs utilizing a comparator and shift-registers [1] suffer from a slow response time during a large/fast change in load current (Iload). Higher sampling frequency (fS) improves the response time, but at the cost of increased power consumption and reduced loop stability. Multi-bit quantizers utilizing ADCs [2-4] can reduce the settling time, however, the presence of a high resolution ADC and the control logic increases the design complexity. Moreover, the ADC resolution limits the maximum fS. In order to overcome the trade-off between speed and power, adaptive sampling techniques were incorporated in [1], [4]. But the overhead of multiple VCOs operating simultaneously and a separate overshoot/droop detection circuitry [1], or an event-driven controller with 7b ADC [4], increase the complexity and power consumption. Furthermore, none of the previous designs incorporated active voltage positioning (AVP), a popular ripple-suppression technique, whereby the LDO output is set slightly above (in low-activity state) or below (in high-activity state) the reference voltage depending on the processor workload conditions [5].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"8 1","pages":"308-310"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90383682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310183
Shih-Hsiung Chien, Yi-Wen Chen, T. Kuo
Low quiescent current (IQ) is critical for Class-D audio amplifiers in mobile devices to extend battery usage time [1], since typical audio signals have a high crest factor of 10 to 20dB. In addition, low distortion is also important for audio fidelity. Distortion sources in closed-loop Class-D amplifiers can be classified into two types. One is attributed to the nonlinearities of PWM modulators and power stages, while the other is due to the aliasing of fed-back PWM high-frequency residuals, the latter of which comprises phase-error and duty-cycle-error distortions [2]. Figure 3.6.1 shows 2nd-order closed-loop amplifiers and existing techniques for enhancing an amplifier's linearity. Increasing the loop filter order to obtain a higher in-band loop gain by using more integrators [3] or the single-amplifier-biquad [4] suppresses all aforementioned distortions except for the phase-error distortion, which can be suppressed by adding a phase-error-free PWM modulator [2]. However, these techniques increase IQ and/or die area due to the additional active circuits and/or several resistors and capacitors. Since phase-error distortion, as well as duty-cycle-error distortion, is caused by the fed-back PWM high-frequency residuals aliasing with the reference triangular wave VTRI, a uniform PWM [5] with a sample-and-hold circuit implemented before the PWM modulation reduces the PWM residuals via an equivalent notch filtering. However, loop stability is affected by the notch filtering unless the PWM switching frequency fSW is increased, but doing so increases power consumption [4]. Though the technique in [1] uses a feed-forward path with a replicated loop filter to eliminate the PWM residuals without affecting loop stability, the replicated loop filter increases both IQ and area.
{"title":"A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reduction","authors":"Shih-Hsiung Chien, Yi-Wen Chen, T. Kuo","doi":"10.1109/ISSCC.2018.8310183","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310183","url":null,"abstract":"Low quiescent current (IQ) is critical for Class-D audio amplifiers in mobile devices to extend battery usage time [1], since typical audio signals have a high crest factor of 10 to 20dB. In addition, low distortion is also important for audio fidelity. Distortion sources in closed-loop Class-D amplifiers can be classified into two types. One is attributed to the nonlinearities of PWM modulators and power stages, while the other is due to the aliasing of fed-back PWM high-frequency residuals, the latter of which comprises phase-error and duty-cycle-error distortions [2]. Figure 3.6.1 shows 2nd-order closed-loop amplifiers and existing techniques for enhancing an amplifier's linearity. Increasing the loop filter order to obtain a higher in-band loop gain by using more integrators [3] or the single-amplifier-biquad [4] suppresses all aforementioned distortions except for the phase-error distortion, which can be suppressed by adding a phase-error-free PWM modulator [2]. However, these techniques increase IQ and/or die area due to the additional active circuits and/or several resistors and capacitors. Since phase-error distortion, as well as duty-cycle-error distortion, is caused by the fed-back PWM high-frequency residuals aliasing with the reference triangular wave VTRI, a uniform PWM [5] with a sample-and-hold circuit implemented before the PWM modulation reduces the PWM residuals via an equivalent notch filtering. However, loop stability is affected by the notch filtering unless the PWM switching frequency fSW is increased, but doing so increases power consumption [4]. Though the technique in [1] uses a feed-forward path with a replicated loop filter to eliminate the PWM residuals without affecting loop stability, the replicated loop filter increases both IQ and area.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"28 1","pages":"60-62"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78834447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310365
Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, C. Yoo
Current-mode DC-DC converters offer various advantages over voltage-mode DC-DC converters such as much simpler frequency compensation, automatic over-current protection, and faster transient response [1,2]. For current-mode control, however, an accurate inductor current sensor is required which can be very sensitive to noise. Another concern in designing a current-mode DC-DC converter is the instability under certain operating conditions known as subharmonic oscillation. A peak-current-mode buck converter, for example, may become unstable when its switching duty cycle is larger than 50% and slope compensation is required to ensure stable operation. While both current-mode and voltage-mode DC-DC converters are conventionally controlled by voltage-domain controllers that use voltage signals as control variables, the works in [3] and [4] have shown that voltage-mode DC-DC converters can also be controlled by time-domain controllers consisting of only time-domain circuits such as voltage-controlled oscillators, voltage-controlled delay lines, and phase detectors (PD). Because time-domain controllers do not use any wide-bandwidth error amplifier, voltage comparator, and passive RC filter required for conventional voltage-domain controllers, they consume much less power and occupy smaller silicon area.
{"title":"A 10MHz time-domain-controlled current-mode buck converter with 8.5% to 93% switching duty cycle","authors":"Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, C. Yoo","doi":"10.1109/ISSCC.2018.8310365","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310365","url":null,"abstract":"Current-mode DC-DC converters offer various advantages over voltage-mode DC-DC converters such as much simpler frequency compensation, automatic over-current protection, and faster transient response [1,2]. For current-mode control, however, an accurate inductor current sensor is required which can be very sensitive to noise. Another concern in designing a current-mode DC-DC converter is the instability under certain operating conditions known as subharmonic oscillation. A peak-current-mode buck converter, for example, may become unstable when its switching duty cycle is larger than 50% and slope compensation is required to ensure stable operation. While both current-mode and voltage-mode DC-DC converters are conventionally controlled by voltage-domain controllers that use voltage signals as control variables, the works in [3] and [4] have shown that voltage-mode DC-DC converters can also be controlled by time-domain controllers consisting of only time-domain circuits such as voltage-controlled oscillators, voltage-controlled delay lines, and phase detectors (PD). Because time-domain controllers do not use any wide-bandwidth error amplifier, voltage comparator, and passive RC filter required for conventional voltage-domain controllers, they consume much less power and occupy smaller silicon area.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"14 1","pages":"424-426"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83357317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310314
Woojun Choi, Yongtae Lee, Seonhong Kim, Sanghoon Lee, Jieun Jang, J. Chun, K. Makinwa, Youngcheol Chae
In microprocessors and DRAMs, on-chip temperature sensors are essential components, ensuring reliability by monitoring thermal gradients and hot spots. Such sensors must be as small as possible, since multiple sensors are required for dense thermal monitoring. However, conventional BJT-based temperature sensors are not compatible with the sub-1V supply of advanced processes. Subthreshold MOSFETs can operate from lower supplies, but at high temperatures their performance is limited by leakage [1,2]. Thermal diffusivity (TD) sensors achieve sub-1V operation and small area with moderate accuracy, but require milliwatts of power [3]. Recently, resistor-based sensors based on RC WienBridge (WB) filters have realized high resolution and energy efficiency [4,5]. Fundamentally, they are robust to process and supply-voltage scaling. However, their readout circuitry has been based on continuous-time (CT) ΔΣ ADCs or frequency-locked loops (FLLs), which require precision analog circuits and occupy considerable area (>0.7mm2).
{"title":"A 0.53pJK2 7000μm2 resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS","authors":"Woojun Choi, Yongtae Lee, Seonhong Kim, Sanghoon Lee, Jieun Jang, J. Chun, K. Makinwa, Youngcheol Chae","doi":"10.1109/ISSCC.2018.8310314","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310314","url":null,"abstract":"In microprocessors and DRAMs, on-chip temperature sensors are essential components, ensuring reliability by monitoring thermal gradients and hot spots. Such sensors must be as small as possible, since multiple sensors are required for dense thermal monitoring. However, conventional BJT-based temperature sensors are not compatible with the sub-1V supply of advanced processes. Subthreshold MOSFETs can operate from lower supplies, but at high temperatures their performance is limited by leakage [1,2]. Thermal diffusivity (TD) sensors achieve sub-1V operation and small area with moderate accuracy, but require milliwatts of power [3]. Recently, resistor-based sensors based on RC WienBridge (WB) filters have realized high resolution and energy efficiency [4,5]. Fundamentally, they are robust to process and supply-voltage scaling. However, their readout circuitry has been based on continuous-time (CT) ΔΣ ADCs or frequency-locked loops (FLLs), which require precision analog circuits and occupy considerable area (>0.7mm2).","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"13 1","pages":"322-324"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89621224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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