Towards a sub-1 V CMOS voltage reference

Abstract

A sub-1-V CMOS voltage reference which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-/spl mu/m CMOS process and gives a temperature coefficient of 4 ppm//spl deg/C in the range of -50/spl deg/C to 150/spl deg/C.