D. Vasilache, M. Chistè, S. Colpo, F. Giacomozzi, B. Margesin
{"title":"Wafer resistivity influence over DRIE processes for TSVs manufacturing","authors":"D. Vasilache, M. Chistè, S. Colpo, F. Giacomozzi, B. Margesin","doi":"10.1109/SMICND.2012.6400662","DOIUrl":null,"url":null,"abstract":"This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.","PeriodicalId":9628,"journal":{"name":"CAS 2012 (International Semiconductor Conference)","volume":"150 1","pages":"175-178"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"CAS 2012 (International Semiconductor Conference)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.2012.6400662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
This paper presents for the first time influence of the silicon resistivity over the DRIE processes. Our aim was to develop a new process for tapered walls through silicon vias (TSVs) with a good control over the walls angle. Different wafer types were used and a dependency of resistivity was found, with an important impact over the TSVs shape. Solution found is presented and experiments performed to obtained designed TSVs.
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