Optimization of Parasitic Inductance for Si-SiC Hybrid Power Module Package

Abstract

The rapid on-off operation of power devices will cause voltage overshoot and oscillation through the parasitic inductance, which will affect the performance and safe operation of the circuit. This paper analyzes the internal package structure of Si-SiC hybrid multi-unit IGBT power integrated module, and the parasitic inductance caused by the module package is discussed. The parasitic inductance of each commutation loop in the three-phase inverter module is very different, which will lead to three-phase imbalance. In this paper, three schemes are used to optimize the parasitic inductance of both the inverter and chopper circuits, including changing the pin position, layout optimization and local double-sides substrate. The results show that, the power commutation loop parasitic inductance in the inverter circuit is reduced by 24.1% on average, and the difference of each phase is reduced from 37.9% to 27.8%. Although the power loop parasitic inductance of the chopper circuit is not optimized, the gate loop inductance of the chopper circuit is reduced by 59.1%, and the common emitter inductance is reduced by 20.9%.