Junho Cheon, Insoo Lee, Changyong Ahn, M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, E. Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong Kang, J. Chun
{"title":"Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology","authors":"Junho Cheon, Insoo Lee, Changyong Ahn, M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, E. Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong Kang, J. Chun","doi":"10.1109/CICC.2015.7338358","DOIUrl":null,"url":null,"abstract":"A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338358","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.
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