Pub Date : 2019-04-01DOI: 10.1109/CICC.2019.8780318
Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel
{"title":"Portable and Scalable High Voltage Circuits for Automotive Applications in BiCMOS Processes","authors":"Sri Navaneeth Easwaran, Samir Camdzic, R. Weigel","doi":"10.1109/CICC.2019.8780318","DOIUrl":"https://doi.org/10.1109/CICC.2019.8780318","url":null,"abstract":"","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"37 1","pages":"1-87"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76921172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/CICC.2017.7993674
Christophe Antoine, M. Tartagni
This session gathers three emerging multidisciplinary applications of electronic circuits: flexible substrates, energy harvesting sensors on power lines and optically-assisted high-bandwidth electronics.
本次会议汇集了三个新兴的多学科电子电路应用:柔性衬底，电力线上的能量收集传感器和光辅助高带宽电子。
{"title":"Session 27 - Technology directions","authors":"Christophe Antoine, M. Tartagni","doi":"10.1109/CICC.2017.7993674","DOIUrl":"https://doi.org/10.1109/CICC.2017.7993674","url":null,"abstract":"This session gathers three emerging multidisciplinary applications of electronic circuits: flexible substrates, energy harvesting sensors on power lines and optically-assisted high-bandwidth electronics.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"30 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85711175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338360
Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, Kenta Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.
{"title":"A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor","authors":"Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Y. Kawamoto, Kenta Takagi, S. Yoshimoto, S. Izumi, K. Nii, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/CICC.2015.7338360","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338360","url":null,"abstract":"This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bitcells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip can operate at a supply voltage of 0.46 V and an access time of 140 ns. The energy minimum point is a supply voltage of 0.54 V and an access time of 55 ns (= 18.2 MHz), at which 298 fJ/cycle in a write operation and 650 fJ/cycle in a read operation are achieved with the help of the majority logic; these factor are 87% and 52% smaller than those in a 28-nm FD-SOI 6T SRAM.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"47 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73831466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338466
Christophe Antoine, R. Muller
For Biomedical sensor systems, there are always a lot of challenges in four major areas, namely the design of the bio-sensors itself, the power management of the implantable devices, the communication with these devices and the signal processing within these devices. In this session, the first paper describes a large (512×576) CMOS ISFET sensor realized in 65nm CMOS technology targeted towards DNA sequencing. It achieves high readout gain (201 mV/ph) and fast readout speed (375 fps). To address the challenges in the power management of implants, a voltage doubling rectifier and regulator combined circuit is described in the second paper. Power conversion efficiency and voltage conversion efficiency are improved by utilizing the voltage regulation transistor also as a passive rectifier. To efficiently utilize the communication bandwidth as well as power available in the implants, compressed-sensing is a hot topic in the biomedical area. The third paper describes a signal processing technique that compresses and also extracts key statistics of the input signal at sampling time. With these statistics, the reconstruction of the signal can be significantly improved (9-18dB) at the receiver. The fourth paper describes a fully-integrated, full-duplex wireless transceiver to address the challenges for high rate data communication (100 Mbps downlink and 500 Mbps uplink) required in some implantable devices. Physical size requirement is reduced by avoiding the use of circulators/diplexers with the antenna for RX and TX being shared.
{"title":"Session 7 — Advances in biomedial sensor systems","authors":"Christophe Antoine, R. Muller","doi":"10.1109/CICC.2015.7338466","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338466","url":null,"abstract":"For Biomedical sensor systems, there are always a lot of challenges in four major areas, namely the design of the bio-sensors itself, the power management of the implantable devices, the communication with these devices and the signal processing within these devices. In this session, the first paper describes a large (512×576) CMOS ISFET sensor realized in 65nm CMOS technology targeted towards DNA sequencing. It achieves high readout gain (201 mV/ph) and fast readout speed (375 fps). To address the challenges in the power management of implants, a voltage doubling rectifier and regulator combined circuit is described in the second paper. Power conversion efficiency and voltage conversion efficiency are improved by utilizing the voltage regulation transistor also as a passive rectifier. To efficiently utilize the communication bandwidth as well as power available in the implants, compressed-sensing is a hot topic in the biomedical area. The third paper describes a signal processing technique that compresses and also extracts key statistics of the input signal at sampling time. With these statistics, the reconstruction of the signal can be significantly improved (9-18dB) at the receiver. The fourth paper describes a fully-integrated, full-duplex wireless transceiver to address the challenges for high rate data communication (100 Mbps downlink and 500 Mbps uplink) required in some implantable devices. Physical size requirement is reduced by avoiding the use of circulators/diplexers with the antenna for RX and TX being shared.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"17 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73836215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338358
Junho Cheon, Insoo Lee, Changyong Ahn, M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, E. Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong Kang, J. Chun
A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.
{"title":"Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology","authors":"Junho Cheon, Insoo Lee, Changyong Ahn, M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, E. Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong Kang, J. Chun","doi":"10.1109/CICC.2015.7338358","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338358","url":null,"abstract":"A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75419676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338381
Tzu-Fan Wu, C. Ho, M. Chen
This paper introduces a different class of ADC architecture that non-uniformly samples the analog input but generates uniform digital output. The proposed non-uniform sampling ADC utilizes 4-bit voltage quantizer and time quantizer with 10 ps accuracy. Combined with the proposed digital anti-aliasing filter, it improves SNR by nearly 30 dB in comparison with a conventional 4-bit uniform sampling ADC. Furthermore, the unwanted blocker signal can be attenuated within this non-uniform sampling ADC architecture without an analog anti-aliasing filter. As a proof of concept, the ADC prototype in 65nm CMOS measures EVM of -27 dB for a 16-QAM input signal under 50-dB higher blocker.
{"title":"A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS","authors":"Tzu-Fan Wu, C. Ho, M. Chen","doi":"10.1109/CICC.2015.7338381","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338381","url":null,"abstract":"This paper introduces a different class of ADC architecture that non-uniformly samples the analog input but generates uniform digital output. The proposed non-uniform sampling ADC utilizes 4-bit voltage quantizer and time quantizer with 10 ps accuracy. Combined with the proposed digital anti-aliasing filter, it improves SNR by nearly 30 dB in comparison with a conventional 4-bit uniform sampling ADC. Furthermore, the unwanted blocker signal can be attenuated within this non-uniform sampling ADC architecture without an analog anti-aliasing filter. As a proof of concept, the ADC prototype in 65nm CMOS measures EVM of -27 dB for a 16-QAM input signal under 50-dB higher blocker.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"31 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75119328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-30DOI: 10.1109/CICC.2015.7338412
Hyung-Min Lee, M. Kiani, Maysam Ghovanloo
Short-range wireless power and data transmission offers a viable mean to power up implantable medical devices (IMDs) with a wide range of power levels and communicate with external units across the skin. To optimize wireless power transfer (WPT), it is key to improve efficiencies in every stage of the power delivery path from external power sources to the IMD, while maintaining robustness and safety against load variations, coil misalignments, and nearby conductive objects. This paper reviews various mechanisms for WPT with focus on link structures and circuit techniques for wirelessly-powered IMDs. Moreover, advanced IMDs require wireless data telemetry (WDT) for wideband bidirectional data communication in the presence of the strong power carrier interference. This paper also discusses several modulation schemes and transceiver circuits for low-power, carrier-less, and robust WDT.
{"title":"Advanced wireless power and data transmission techniques for implantable medical devices","authors":"Hyung-Min Lee, M. Kiani, Maysam Ghovanloo","doi":"10.1109/CICC.2015.7338412","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338412","url":null,"abstract":"Short-range wireless power and data transmission offers a viable mean to power up implantable medical devices (IMDs) with a wide range of power levels and communicate with external units across the skin. To optimize wireless power transfer (WPT), it is key to improve efficiencies in every stage of the power delivery path from external power sources to the IMD, while maintaining robustness and safety against load variations, coil misalignments, and nearby conductive objects. This paper reviews various mechanisms for WPT with focus on link structures and circuit techniques for wirelessly-powered IMDs. Moreover, advanced IMDs require wireless data telemetry (WDT) for wideband bidirectional data communication in the presence of the strong power carrier interference. This paper also discusses several modulation schemes and transceiver circuits for low-power, carrier-less, and robust WDT.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"43 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84304663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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