T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman
{"title":"A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration","authors":"T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman","doi":"10.1109/CICC.2015.7338371","DOIUrl":null,"url":null,"abstract":"A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75\" traces) and 1.9pJ/bit (10\" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"166 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338371","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75" traces) and 1.9pJ/bit (10" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.
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