A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging

Abstract

High-density multi-channel neural recording is critical to driving advances in neuroscience and neuroengineering through increasing the spatial resolution and dynamic range of brain-machine interfaces. Neural-signal-acquisition ICs have conventionally been designed composed of two distinct functional blocks per recording channel: a low-noise amplifier front-end (AFE), and an analog-digital converter (ADC) [1,2]. Hybrid architectures utilizing oversampling ADCs with digital feedback [3-5] have seen recent adoption due to their increased power and area efficiency. Still, input dynamic range (DR) is relatively limited due to aggressive supply voltage scaling and/or kT/C sampling noise. This paper presents a neural-recording ADC chip with 92dB input dynamic range and 0.99μVrms of noise at 0.8μW power consumption per channel over 500Hz signal bandwidth, owing to 1) a predictive digital autoranging (PDA) scheme in a hybrid analog-digital 2nd-order oversampling ADC architecture, 2) no specific sampling process through capacitors, avoiding kT/C noise altogether. Digitally predicting the analog input at 12b resolution from a 1b quantization of the continuously integrated residue at effective 32 oversampling ratio (OSR), the PDA handles a ±130mV electrode differential offset (EDO) and recovers from >200mVpp transient artifacts within <1ms. Furthermore, using digital circuits for integration ensures the architecture benefits from process scaling and the resulting compactness makes it suitable for incorporation in high-density recording arrays.