Passive compensation for high performance inter-chip communication

Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng
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引用次数: 5

Abstract

This paper develops a novel high-speed inter-chip serial signaling scheme with leakage shunt resistors and termination resistors between the signal trace and the ground. For given abstract topology transmission line based on the data for IBM high-end AS/400 system[1] [2], we put termination resistors at the end of receiver and adjust the shunt and termination resistors value to get the optimal distortion-less transmission line. Analytical formulas are derived to predict the worst case jitter and eye-opening based on bitonic step Response Assumption[3]. Our schemes and the other two comparison cases are discussed.
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无源补偿的高性能芯片间通信
本文提出了一种新的高速芯片间串行信号传输方案,该方案在信号走线与地之间采用漏电分流电阻和端接电阻。基于IBM高端AS/400系统[1][2]的数据,对于给定的抽象拓扑传输线,我们在接收端放置端接电阻,通过调整分流和端接电阻的值来获得最佳的无失真传输线。基于双音阶跃响应假设,推导出最坏情况下的抖动和大眼预测的解析公式[3]。讨论了我们的方案和另外两个比较案例。
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