Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, M. Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille
{"title":"A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level","authors":"Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, M. Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille","doi":"10.1109/ISSCC.2018.8310181","DOIUrl":null,"url":null,"abstract":"Conventional Class-D amplifiers, although more power efficient than Class-AB amplifiers, typically do not deliver the same audio quality. The non-ideal switching behavior of the output power stages can degrade the linearity, noise and power-supply-rejection-ratio (PSRR) performance of Class-D amplifiers if employed in open-loop configurations [1]. Closed-loop Class-D amplifiers shape the non-idealities of the power amplifiers (PAs) and provide improved performance [2]. Conventional analog feedback amplifiers (AFAs) sense the PA output and feed it back to compare with the audio input signal in the analog domain. Compared with AFAs, digital feedback amplifiers (DFAs) have emerged with benefits of improved control of the loop filter and pulse-width modulation (PWM) in the digital domain. However, the DFA architecture usually demands a high-performance analog-to-digital converter (ADC) to digitize the PA output in the feedback path; This ADC's non-idealities may become the bottleneck of the system [3]. In this paper, a 2-channel Class-D digital error-feedback amplifier (DEFA) with a peak THD+N of 0.0013% is presented. A series of proposed techniques enable the DEFA to maintain its performance up to the maximum power level available.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"20 1","pages":"56-58"},"PeriodicalIF":0.0000,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2018.8310181","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
Conventional Class-D amplifiers, although more power efficient than Class-AB amplifiers, typically do not deliver the same audio quality. The non-ideal switching behavior of the output power stages can degrade the linearity, noise and power-supply-rejection-ratio (PSRR) performance of Class-D amplifiers if employed in open-loop configurations [1]. Closed-loop Class-D amplifiers shape the non-idealities of the power amplifiers (PAs) and provide improved performance [2]. Conventional analog feedback amplifiers (AFAs) sense the PA output and feed it back to compare with the audio input signal in the analog domain. Compared with AFAs, digital feedback amplifiers (DFAs) have emerged with benefits of improved control of the loop filter and pulse-width modulation (PWM) in the digital domain. However, the DFA architecture usually demands a high-performance analog-to-digital converter (ADC) to digitize the PA output in the feedback path; This ADC's non-idealities may become the bottleneck of the system [3]. In this paper, a 2-channel Class-D digital error-feedback amplifier (DEFA) with a peak THD+N of 0.0013% is presented. A series of proposed techniques enable the DEFA to maintain its performance up to the maximum power level available.