Exploration of Design Optimizations for STTMRAM as L1 Cache

Abstract

With the advent of data-intensive workloads, much effort has been put forth in recent years in designing memory architectures capable of storing massive data and, at the same time, processing it with lower latency. Non Volatile Memory(NVM) has emerged as a promising technology in meeting this challenge as possible on-chip memories due to its very high density and low leakage powers. Compared to other NVMs, Spin Transfer Torque Magnetic RAM(STTMRAM) has better endurance, lower latency values, and desired asymmetricity in the read & write operations. It is of immense importance that the suitability of using STTMRAM as a Level 1 cache with different design optimization strategies is properly explored. In this paper, we study the power and execution time of the design strategies that optimize read & write latency, dynamic energy, and energy-delay product(EDP). We seek the opportunity to study the performance of these design optimizations against specific memory intense workloads. The first part of our study compares the performance improvement of these design optimizations against SRAM memories. In the second part, we explore regular cache features like block size and associativity variations. Our study reveals that write dynamic energy optimizations have very low static power dissipation; read/write latency optimizations have the best latency values but relatively poor static power dissipation values. Energy-delay product optimization is found to be an optimal solution. The design space exploration carried out offers insight into developing novel application-specific memory systems and motivates research in circuit-level optimizations for future architectures.