Elastic adaptive prefetching for non-volatile cache in IoT terminals

Abstract

STT-RAM with high storage density, near-zero leakage energy and CMOS compatibility is regarded as a replacement for SRAM to build large-sized cache, which can effectively alleviate the “memory wall” and improve computing power of IoT terminals. The state-of-the-art Near-Side Prefetch Throttling (NST) oriented to SRAM cache can effectively hide the access latency of off-chip memory. However, it also shows some inadaptability to the long write latency and high write energy of STT-RAM cache. The NST algorithm can not timely alleviate the cache congestion caused by STT-RAM long write latency, moreover, if the STT-RAM cache is congested, adjusting the prefetch distance is invalid to improve the prefetch timeliness. In response to the above problems, this paper novelly proposes a periodic and real-time complementary prefetch algorithm called ENCP for STT-RAM cache. Experiments show that, compared to the best- performed STREAM prefetcher, ENCP can reduce the write energy of STTRAM cache by 8.3% on average and 23% the most and improve the CPU IPC performance by 0.46% on average and 3.1% the most. And the ENCP has better performance and lower dynamic energy compared with NST with almost the same hardware overhead.