Implementation of high-performance and highly efficient computational modules using binary tree structures at the device level

Abstract

A novel approach to build a full-adder circuit is presented using the modified binary tree. In this approach, the full adder can take only 15 transistors. In the residue-number-system-based digital signal processing architectures, look-up tables are an important computational element. Using the modified binary tree, an efficient row/column decoder is proposed for the look-up table implementation. It is observed that the look-up table based on the conventional approach occupies 26% more area and takes 1.5 ns more access time than the look-up table based on the modified binary tree.<>