Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation

Abstract

This paper proposes a two-dimensional parity-based concurrent error detection method for AES algorithm against differential fault attack. Compared with previous parity-based CED methods, this scheme is able to detect errors in both horizontal and vertical direction in data matrix, therefore it has much higher fault coverage of multiple errors while remains 100% coverage of odd-bit errors. Since all of the parity calculation modules can be used for both horizontal and vertical parity computation, hardware cost of this two-dimensional parity-based CED method is 18%(maximal) higher than those of the traditional methods, whereas the critical path and throughput of this approach remain the same as the ones of traditional ways. It is a novel CED method for AES algorithm against differential fault attack, due to its high efficiency and low cost.