Chong Wang, E. Simoen, A. Alireza, S. Sioncke, N. Collaert, C. Claeys, Wei Li
{"title":"Deep level investigation of INGAAS on INP layer","authors":"Chong Wang, E. Simoen, A. Alireza, S. Sioncke, N. Collaert, C. Claeys, Wei Li","doi":"10.1109/CSTIC.2017.7919841","DOIUrl":null,"url":null,"abstract":"Deep level traps in lattice-matched In0.47Ga0.53As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al2O3/InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"150 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2017.7919841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Deep level traps in lattice-matched In0.47Ga0.53As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al2O3/InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior.
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