External memory interface for RISC controller on reconfigurable hardware logic

Suyash Toro, Sushma Wadar, Y. Chavan, S. Patil, D. Bormane, A. Patil
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引用次数: 1

Abstract

Development in VLSI technology and its implementation leading to optimization of various systems related with prime parameters such as power, speed and area has been achieved. As the consumer electronics market is growing very rapidly, RISC processors with additional features required to be implemented are also demanding. The RISC processor supports many applications with its features, but the feature like external memory interface which is the requirement for some of the applications is limiting factor and has been given due weightage in this paper. This interface of external memory with the RISC processor is targeted to be performed in stipulated time span with the required control signals. The additional hardware required for interfacing the external memory does not affect the timing required for accessing the data from it. The timing analysis with the hardware targeted technology has been done and discussed. This paper presents the simulation of external memory interfacing of 8-bit PIC microcontroller using Xilinx 10.1.
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RISC控制器在可重构硬件逻辑上的外部存储器接口
VLSI技术的发展及其实现导致与功率,速度和面积等主要参数相关的各种系统的优化已经实现。随着消费电子市场的快速增长,RISC处理器的附加功能要求也越来越高。RISC处理器以其自身的特性支持多种应用,但某些应用需要的外部存储器接口等特性是限制因素,本文对此给予了应有的重视。这种外部存储器与RISC处理器的接口旨在在规定的时间范围内与所需的控制信号一起执行。连接外部存储器所需的额外硬件不会影响从外部存储器访问数据所需的时间。利用硬件定向技术进行了时序分析并进行了讨论。本文采用Xilinx 10.1对8位PIC单片机的外部存储器接口进行了仿真。
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