Suyash Toro, Sushma Wadar, Y. Chavan, S. Patil, D. Bormane, A. Patil
{"title":"External memory interface for RISC controller on reconfigurable hardware logic","authors":"Suyash Toro, Sushma Wadar, Y. Chavan, S. Patil, D. Bormane, A. Patil","doi":"10.1109/ICAECCT.2016.7942631","DOIUrl":null,"url":null,"abstract":"Development in VLSI technology and its implementation leading to optimization of various systems related with prime parameters such as power, speed and area has been achieved. As the consumer electronics market is growing very rapidly, RISC processors with additional features required to be implemented are also demanding. The RISC processor supports many applications with its features, but the feature like external memory interface which is the requirement for some of the applications is limiting factor and has been given due weightage in this paper. This interface of external memory with the RISC processor is targeted to be performed in stipulated time span with the required control signals. The additional hardware required for interfacing the external memory does not affect the timing required for accessing the data from it. The timing analysis with the hardware targeted technology has been done and discussed. This paper presents the simulation of external memory interfacing of 8-bit PIC microcontroller using Xilinx 10.1.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"446 1","pages":"455-460"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAECCT.2016.7942631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Development in VLSI technology and its implementation leading to optimization of various systems related with prime parameters such as power, speed and area has been achieved. As the consumer electronics market is growing very rapidly, RISC processors with additional features required to be implemented are also demanding. The RISC processor supports many applications with its features, but the feature like external memory interface which is the requirement for some of the applications is limiting factor and has been given due weightage in this paper. This interface of external memory with the RISC processor is targeted to be performed in stipulated time span with the required control signals. The additional hardware required for interfacing the external memory does not affect the timing required for accessing the data from it. The timing analysis with the hardware targeted technology has been done and discussed. This paper presents the simulation of external memory interfacing of 8-bit PIC microcontroller using Xilinx 10.1.