Depletion-mode MOS capacitor modeling investigation

Abstract

A depletion-mode MOS (DMOS) capacitor modeling methodology with high accuracy and feasibility is proposed. Currently, it is lack of compact model relevant DMOS capacitor modeling but it is significant importance in A/D converters (ADCs) for CMOS image sensor circuit. This modeling methodology not only could provide good accuracy on geometry scaling but also with voltage and temperature sensitivity.