Improvement on the learning performance of multiplierless multilayer neural network

Abstract

In this paper, improved multiplierless multilayer neural network (MNN) with on-chip learning is proposed. Using three-state function as the activating function, multipliers are replaced by much simpler circuit. The back-propagation algorithm is modified to have no multiplier and the algorithm is implemented with pulse mode operation. This learning circuit is modified to improve the rate of successful learning. The derivative function of neurons which is used in the learning algorithm is changed for the higher learning rate. The modification is very simple, and the additional circuit for this modification is very small. To verify the feasibility of the proposed method, the modified MNN is implemented on FPGAs and tested by experiment, and the detail of the learning performance is tested by computer simulations. These results show that the learning rate can be greatly improved by using the proposed MNN architecture. Also, the experimental result shows that the proposed MNN has a very fast operation of 17.9/spl times/10/sup 6/ connections per second (CPS) and 11.7/spl times/10/sup 6/ connection updates per second (CUPS).