SoC-based Architecture for General Purpose Real-Time Histogram Computation

E. Ronconi, N. Corna, S. Salgaro, F. Garzetti, N. Lusardi, L. Bucci, A. Geraci
{"title":"SoC-based Architecture for General Purpose Real-Time Histogram Computation","authors":"E. Ronconi, N. Corna, S. Salgaro, F. Garzetti, N. Lusardi, L. Bucci, A. Geraci","doi":"10.1109/NSS/MIC42677.2020.9508087","DOIUrl":null,"url":null,"abstract":"In this contribution we present a novel implementation of a firmware and software bundle for the computation of real-time histograms based on a System-on-Chip (SoC) Linux-based platform. Histograms are basic instruments that turn out to be of fundamental help when it comes not only to single-shot events, but also to collection and elaboration of big amount of data, their shaping and statistical insights coming from the collected measures. Industry and Academia have already proposed many solutions to this need, both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) IP-Cores. However, despite being mostly satisfying in performance, these solutions often lack ease of use, upgrade and interfacing. Moreover, in this particular application, large storage capabilities are needed, in order to guarantee the user the possibility to build large enough histograms. To solve these issues, we present a hybrid hardware and software implementation of a Histogram Maker in an FPGA-based SoC. Its main features are the large available memory accessible through a Direct Memory Access (DMA), the low amount of consumed FPGA resources of the actual hardware Histogram (Histo-Pack), the real-time behavior and the simplified, yet efficient, interface to the ARM core in the Xilinx SoC, hosting a Linux-based Operating System. A set of IP-Cores and libraries relaxes the effort for the interfacing between the two worlds, so that the user-friendly Processing System can be connected to the programmable logic part to exploit its high-performance in an easy and flexible way. The system has been successfully validated on Xilinx Zynq-7000 and Zynq UltraScale+ devices. This opens new opportunities for simple data transfer through advanced interfaces and protocols, data elaboration and analysis, with no need for complex hardware on the Programmable Logic part. The system is able to receive up to 0.3 Gsps with a refresh rate of 1ms.","PeriodicalId":6760,"journal":{"name":"2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","volume":"93 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSS/MIC42677.2020.9508087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

In this contribution we present a novel implementation of a firmware and software bundle for the computation of real-time histograms based on a System-on-Chip (SoC) Linux-based platform. Histograms are basic instruments that turn out to be of fundamental help when it comes not only to single-shot events, but also to collection and elaboration of big amount of data, their shaping and statistical insights coming from the collected measures. Industry and Academia have already proposed many solutions to this need, both in full-custom Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs) IP-Cores. However, despite being mostly satisfying in performance, these solutions often lack ease of use, upgrade and interfacing. Moreover, in this particular application, large storage capabilities are needed, in order to guarantee the user the possibility to build large enough histograms. To solve these issues, we present a hybrid hardware and software implementation of a Histogram Maker in an FPGA-based SoC. Its main features are the large available memory accessible through a Direct Memory Access (DMA), the low amount of consumed FPGA resources of the actual hardware Histogram (Histo-Pack), the real-time behavior and the simplified, yet efficient, interface to the ARM core in the Xilinx SoC, hosting a Linux-based Operating System. A set of IP-Cores and libraries relaxes the effort for the interfacing between the two worlds, so that the user-friendly Processing System can be connected to the programmable logic part to exploit its high-performance in an easy and flexible way. The system has been successfully validated on Xilinx Zynq-7000 and Zynq UltraScale+ devices. This opens new opportunities for simple data transfer through advanced interfaces and protocols, data elaboration and analysis, with no need for complex hardware on the Programmable Logic part. The system is able to receive up to 0.3 Gsps with a refresh rate of 1ms.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于soc的通用实时直方图计算体系结构
在这篇文章中,我们提出了一种基于片上系统(SoC) linux平台的实时直方图计算的固件和软件包的新实现。直方图是一种基本的工具,不仅在处理单次事件时,而且在收集和阐述大量数据时,直方图是一种基本的帮助,它们的形成和统计见解来自于收集的测量。业界和学术界已经针对这一需求提出了许多解决方案,包括全定制专用集成电路(asic)和现场可编程门阵列(fpga) ip核。然而,尽管这些解决方案在性能上大多令人满意,但它们往往缺乏易用性、升级和接口。此外,在这个特定的应用程序中,为了保证用户能够构建足够大的直方图,需要大的存储能力。为了解决这些问题,我们在基于fpga的SoC中提出了直方图生成器的混合硬件和软件实现。它的主要特点是通过直接内存访问(DMA)可以访问大量可用内存,实际硬件直方图(Histogram - pack)消耗的FPGA资源较少,实时行为和Xilinx SoC中ARM核心的简化但高效的接口,托管基于linux的操作系统。一组ip核和库减轻了两个世界之间的接口工作,使用户友好的处理系统可以连接到可编程逻辑部分,以一种简单灵活的方式发挥其高性能。该系统已在Xilinx Zynq-7000和Zynq UltraScale+设备上成功验证。这为通过高级接口和协议进行简单数据传输、数据细化和分析提供了新的机会,而无需在可编程逻辑部分使用复杂的硬件。该系统能够以1ms的刷新率接收高达0.3 Gsps的信号。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Performance of Dual-Ended Readout PET Detectors Based on SiPMs with Different Microcell Sizes Neural Network-based Inter-crystal Scatter Event Positioning in a PET System Design Based on 3D Position Sensitive Detectors An e-LINAC driven PGNAA system for concealed drug inspection Design of a Multi-Technology Pre-Clinical SPECT System Comprehensive Simulation and Design of 3D Silicon Sensors for Enhanced Timing Performance
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1