Efficient bit-serial systolic array for division over GF(2m)

Abstract

In this paper, we propose a new bit-serial systolic array for computing division over GF(2") using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2"). Analysis shows that the proposed array provides a significant reduction in both chip area and computational. delay time compared to previously proposed systolic arrays with the same U 0 format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuit of elliptic curve cryptosystems (ECC).