R. Seidel, G. Bonsdorf, E. Clauss, J. Daleiden-, K. Donegan, F. Feustel, M. Hauschildt, B. Hintze, F. Koschinsky, G. Marxsen, R. Naumann, C. Peters, U. Queitsch, G. Talut, D. Theiss, M. Zinke
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引用次数: 0
Abstract
Substantial improvements have been achieved in interconnects with 90nm pitch. Solutions for an optimized patterning and metallization will be presented (e.g. ULK treatments during etch, complete metal hard-mask removal by wet-clean, ultra-thin PVD liner). A particular challenge for a semiconductor foundry is the band-width of customer specific designs and requirements. Novel design dependent process strategies have been developed. Transferring this learning will be crucial for a successful ramp of subsequent technologies.
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